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75051ce4c5
This aligns the iavf_debug() macro with the other Intel drivers. Add the bus number, bus_id field to i40e_bus_info so output shows each physical port(i.e func) in following format: [[[[<domain>]:]<bus>]:][<slot>][.[<func>]] domains are numbered from 0 to ffff), bus (0-ff), slot (0-1f) and function (0-7). Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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#ifndef _IAVF_OSDEP_H_
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#define _IAVF_OSDEP_H_
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#include <linux/types.h>
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#include <linux/if_ether.h>
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#include <linux/if_vlan.h>
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#include <linux/tcp.h>
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#include <linux/pci.h>
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/* get readq/writeq support for 32 bit kernels, use the low-first version */
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#include <linux/io-64-nonatomic-lo-hi.h>
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/* File to be the magic between shared code and
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* actual OS primitives
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*/
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#define hw_dbg(hw, S, A...) do {} while (0)
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#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
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#define rd32(a, reg) readl((a)->hw_addr + (reg))
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#define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
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#define rd64(a, reg) readq((a)->hw_addr + (reg))
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#define iavf_flush(a) readl((a)->hw_addr + IAVF_VFGEN_RSTAT)
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/* memory allocation tracking */
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struct iavf_dma_mem {
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void *va;
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dma_addr_t pa;
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u32 size;
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};
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#define iavf_allocate_dma_mem(h, m, unused, s, a) \
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iavf_allocate_dma_mem_d(h, m, s, a)
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#define iavf_free_dma_mem(h, m) iavf_free_dma_mem_d(h, m)
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struct iavf_virt_mem {
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void *va;
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u32 size;
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};
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#define iavf_allocate_virt_mem(h, m, s) iavf_allocate_virt_mem_d(h, m, s)
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#define iavf_free_virt_mem(h, m) iavf_free_virt_mem_d(h, m)
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#define iavf_debug(h, m, s, ...) \
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do { \
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if (((m) & (h)->debug_mask)) \
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pr_info("iavf %02x:%02x.%x " s, \
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(h)->bus.bus_id, (h)->bus.device, \
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(h)->bus.func, ##__VA_ARGS__); \
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} while (0)
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#endif /* _IAVF_OSDEP_H_ */
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