Asutosh Das 2468da61ea scsi: ufs: core: mcq: Configure operation and runtime interface ... Runtime and operation registers are defined per Submission and Completion queue. The location of these registers is not defined in the spec; meaning the offsets and stride may vary for different HC vendors. Establish the stride, base address, and doorbell address offsets from vendor host driver and program it. Co-developed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Asutosh Das <quic_asutoshd@quicinc.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>		2023-01-13 21:03:37 -05:00
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ufs_quirks.h
ufs.h	scsi: ufs: core: mcq: Calculate queue depth	2023-01-13 21:03:37 -05:00
ufshcd.h	scsi: ufs: core: mcq: Configure operation and runtime interface	2023-01-13 21:03:37 -05:00
ufshci.h	scsi: ufs: core: mcq: Configure operation and runtime interface	2023-01-13 21:03:37 -05:00
unipro.h	scsi: ufs: ufs-mediatek: Introduce workaround for power mode change	2022-06-16 22:08:43 -04:00