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d2109a1219
Use access helper irq_data_get_affinity_mask() to hide implementation details of struct irq_desc. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: James E.J. Bottomley <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Link: http://lkml.kernel.org/r/1433145945-789-24-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
1006 lines
29 KiB
C
1006 lines
29 KiB
C
/*
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** I/O Sapic Driver - PCI interrupt line support
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**
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** (c) Copyright 1999 Grant Grundler
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** (c) Copyright 1999 Hewlett-Packard Company
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** The I/O sapic driver manages the Interrupt Redirection Table which is
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** the control logic to convert PCI line based interrupts into a Message
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** Signaled Interrupt (aka Transaction Based Interrupt, TBI).
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**
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** Acronyms
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** --------
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** HPA Hard Physical Address (aka MMIO address)
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** IRQ Interrupt ReQuest. Implies Line based interrupt.
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** IRT Interrupt Routing Table (provided by PAT firmware)
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** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA
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** table which is implemented in I/O SAPIC.
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** ISR Interrupt Service Routine. aka Interrupt handler.
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** MSI Message Signaled Interrupt. PCI 2.2 functionality.
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** aka Transaction Based Interrupt (or TBI).
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** PA Precision Architecture. HP's RISC architecture.
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** RISC Reduced Instruction Set Computer.
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**
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**
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** What's a Message Signalled Interrupt?
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** -------------------------------------
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** MSI is a write transaction which targets a processor and is similar
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** to a processor write to memory or MMIO. MSIs can be generated by I/O
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** devices as well as processors and require *architecture* to work.
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**
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** PA only supports MSI. So I/O subsystems must either natively generate
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** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs
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** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which
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** acts on behalf of a processor.
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**
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** MSI allows any I/O device to interrupt any processor. This makes
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** load balancing of the interrupt processing possible on an SMP platform.
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** Interrupts are also ordered WRT to DMA data. It's possible on I/O
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** coherent systems to completely eliminate PIO reads from the interrupt
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** path. The device and driver must be designed and implemented to
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** guarantee all DMA has been issued (issues about atomicity here)
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** before the MSI is issued. I/O status can then safely be read from
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** DMA'd data by the ISR.
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**
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**
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** PA Firmware
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** -----------
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** PA-RISC platforms have two fundamentally different types of firmware.
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** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
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** and BARs similar to a traditional PC BIOS.
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** The newer "PAT" firmware supports PDC calls which return tables.
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** PAT firmware only initializes the PCI Console and Boot interface.
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** With these tables, the OS can program all other PCI devices.
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**
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** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
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** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
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** input line. If the IRT is not available, this driver assumes
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** INTERRUPT_LINE register has been programmed by firmware. The latter
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** case also means online addition of PCI cards can NOT be supported
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** even if HW support is present.
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**
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** All platforms with PAT firmware to date (Oct 1999) use one Interrupt
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** Routing Table for the entire platform.
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**
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** Where's the iosapic?
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** --------------------
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** I/O sapic is part of the "Core Electronics Complex". And on HP platforms
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** it's integrated as part of the PCI bus adapter, "lba". So no bus walk
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** will discover I/O Sapic. I/O Sapic driver learns about each device
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** when lba driver advertises the presence of the I/O sapic by calling
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** iosapic_register().
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**
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**
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** IRQ handling notes
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** ------------------
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** The IO-SAPIC can indicate to the CPU which interrupt was asserted.
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** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per
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** IO-SAPIC interrupt and call the device driver's handler directly.
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** The IO-SAPIC driver hijacks the CPU interrupt handler so it can
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** issue the End Of Interrupt command to the IO-SAPIC.
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**
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** Overview of exported iosapic functions
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** --------------------------------------
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** (caveat: code isn't finished yet - this is just the plan)
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**
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** iosapic_init:
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** o initialize globals (lock, etc)
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** o try to read IRT. Presence of IRT determines if this is
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** a PAT platform or not.
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**
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** iosapic_register():
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** o create iosapic_info instance data structure
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** o allocate vector_info array for this iosapic
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** o initialize vector_info - read corresponding IRdT?
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**
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** iosapic_xlate_pin: (only called by fixup_irq for PAT platform)
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** o intr_pin = read cfg (INTERRUPT_PIN);
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** o if (device under PCI-PCI bridge)
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** translate slot/pin
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**
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** iosapic_fixup_irq:
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** o if PAT platform (IRT present)
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** intr_pin = iosapic_xlate_pin(isi,pcidev):
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** intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin)
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** save IRT entry into vector_info later
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** write cfg INTERRUPT_LINE (with intr_line)?
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** else
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** intr_line = pcidev->irq
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** IRT pointer = NULL
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** endif
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** o locate vector_info (needs: isi, intr_line)
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** o allocate processor "irq" and get txn_addr/data
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** o request_irq(processor_irq, iosapic_interrupt, vector_info,...)
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**
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** iosapic_enable_irq:
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** o clear any pending IRQ on that line
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** o enable IRdT - call enable_irq(vector[line]->processor_irq)
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** o write EOI in case line is already asserted.
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**
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** iosapic_disable_irq:
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** o disable IRdT - call disable_irq(vector[line]->processor_irq)
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*/
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/* FIXME: determine which include files are really needed */
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <asm/byteorder.h> /* get in-line asm for swab */
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#include <asm/pdc.h>
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#include <asm/pdcpat.h>
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#include <asm/page.h>
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#include <asm/io.h> /* read/write functions */
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#ifdef CONFIG_SUPERIO
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#include <asm/superio.h>
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#endif
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#include <asm/ropes.h>
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#include "iosapic_private.h"
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#define MODULE_NAME "iosapic"
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/* "local" compile flags */
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#undef PCI_BRIDGE_FUNCS
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#undef DEBUG_IOSAPIC
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#undef DEBUG_IOSAPIC_IRT
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#ifdef DEBUG_IOSAPIC
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#define DBG(x...) printk(x)
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#else /* DEBUG_IOSAPIC */
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#define DBG(x...)
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#endif /* DEBUG_IOSAPIC */
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#ifdef DEBUG_IOSAPIC_IRT
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#define DBG_IRT(x...) printk(x)
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#else
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#define DBG_IRT(x...)
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#endif
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#ifdef CONFIG_64BIT
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#define COMPARE_IRTE_ADDR(irte, hpa) ((irte)->dest_iosapic_addr == (hpa))
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#else
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#define COMPARE_IRTE_ADDR(irte, hpa) \
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((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL))
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#endif
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#define IOSAPIC_REG_SELECT 0x00
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#define IOSAPIC_REG_WINDOW 0x10
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#define IOSAPIC_REG_EOI 0x40
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#define IOSAPIC_REG_VERSION 0x1
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#define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
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#define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
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static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg)
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{
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writel(reg, iosapic + IOSAPIC_REG_SELECT);
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return readl(iosapic + IOSAPIC_REG_WINDOW);
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}
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static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val)
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{
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writel(reg, iosapic + IOSAPIC_REG_SELECT);
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writel(val, iosapic + IOSAPIC_REG_WINDOW);
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}
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#define IOSAPIC_VERSION_MASK 0x000000ff
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#define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK))
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#define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
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#define IOSAPIC_MAX_ENTRY_SHIFT 0x10
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#define IOSAPIC_IRDT_MAX_ENTRY(ver) \
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(int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
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/* bits in the "low" I/O Sapic IRdT entry */
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#define IOSAPIC_IRDT_ENABLE 0x10000
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#define IOSAPIC_IRDT_PO_LOW 0x02000
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#define IOSAPIC_IRDT_LEVEL_TRIG 0x08000
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#define IOSAPIC_IRDT_MODE_LPRI 0x00100
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/* bits in the "high" I/O Sapic IRdT entry */
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#define IOSAPIC_IRDT_ID_EID_SHIFT 0x10
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static DEFINE_SPINLOCK(iosapic_lock);
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static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
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{
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__raw_writel(data, addr);
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}
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/*
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** REVISIT: future platforms may have more than one IRT.
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** If so, the following three fields form a structure which
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** then be linked into a list. Names are chosen to make searching
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** for them easy - not necessarily accurate (eg "cell").
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**
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** Alternative: iosapic_info could point to the IRT it's in.
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** iosapic_register() could search a list of IRT's.
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*/
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static struct irt_entry *irt_cell;
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static size_t irt_num_entry;
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static struct irt_entry *iosapic_alloc_irt(int num_entries)
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{
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unsigned long a;
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/* The IRT needs to be 8-byte aligned for the PDC call.
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* Normally kmalloc would guarantee larger alignment, but
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* if CONFIG_DEBUG_SLAB is enabled, then we can get only
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* 4-byte alignment on 32-bit kernels
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*/
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a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL);
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a = (a + 7UL) & ~7UL;
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return (struct irt_entry *)a;
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}
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/**
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* iosapic_load_irt - Fill in the interrupt routing table
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* @cell_num: The cell number of the CPU we're currently executing on
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* @irt: The address to place the new IRT at
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* @return The number of entries found
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*
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* The "Get PCI INT Routing Table Size" option returns the number of
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* entries in the PCI interrupt routing table for the cell specified
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* in the cell_number argument. The cell number must be for a cell
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* within the caller's protection domain.
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*
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* The "Get PCI INT Routing Table" option returns, for the cell
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* specified in the cell_number argument, the PCI interrupt routing
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* table in the caller allocated memory pointed to by mem_addr.
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* We assume the IRT only contains entries for I/O SAPIC and
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* calculate the size based on the size of I/O sapic entries.
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*
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* The PCI interrupt routing table entry format is derived from the
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* IA64 SAL Specification 2.4. The PCI interrupt routing table defines
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* the routing of PCI interrupt signals between the PCI device output
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* "pins" and the IO SAPICs' input "lines" (including core I/O PCI
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* devices). This table does NOT include information for devices/slots
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* behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec.
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* for the architected method of routing of IRQ's behind PPB's.
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*/
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static int __init
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iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
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{
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long status; /* PDC return value status */
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struct irt_entry *table; /* start of interrupt routing tbl */
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unsigned long num_entries = 0UL;
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BUG_ON(!irt);
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if (is_pdc_pat()) {
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/* Use pat pdc routine to get interrupt routing table size */
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DBG("calling get_irt_size (cell %ld)\n", cell_num);
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status = pdc_pat_get_irt_size(&num_entries, cell_num);
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DBG("get_irt_size: %ld\n", status);
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BUG_ON(status != PDC_OK);
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BUG_ON(num_entries == 0);
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/*
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** allocate memory for interrupt routing table
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** This interface isn't really right. We are assuming
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** the contents of the table are exclusively
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** for I/O sapic devices.
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*/
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table = iosapic_alloc_irt(num_entries);
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if (table == NULL) {
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printk(KERN_WARNING MODULE_NAME ": read_irt : can "
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"not alloc mem for IRT\n");
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return 0;
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}
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/* get PCI INT routing table */
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status = pdc_pat_get_irt(table, cell_num);
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DBG("pdc_pat_get_irt: %ld\n", status);
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WARN_ON(status != PDC_OK);
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} else {
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/*
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** C3000/J5000 (and similar) platforms with Sprockets PDC
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** will return exactly one IRT for all iosapics.
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** So if we have one, don't need to get it again.
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*/
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if (irt_cell)
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return 0;
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/* Should be using the Elroy's HPA, but it's ignored anyway */
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status = pdc_pci_irt_size(&num_entries, 0);
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DBG("pdc_pci_irt_size: %ld\n", status);
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if (status != PDC_OK) {
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/* Not a "legacy" system with I/O SAPIC either */
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return 0;
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}
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BUG_ON(num_entries == 0);
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table = iosapic_alloc_irt(num_entries);
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if (!table) {
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printk(KERN_WARNING MODULE_NAME ": read_irt : can "
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"not alloc mem for IRT\n");
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return 0;
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}
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/* HPA ignored by this call too. */
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status = pdc_pci_irt(num_entries, 0, table);
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BUG_ON(status != PDC_OK);
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}
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/* return interrupt table address */
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*irt = table;
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#ifdef DEBUG_IOSAPIC_IRT
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{
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struct irt_entry *p = table;
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int i;
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printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
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printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
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table,
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num_entries,
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(int) sizeof(struct irt_entry));
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for (i = 0 ; i < num_entries ; i++, p++) {
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printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
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p->entry_type, p->entry_length, p->interrupt_type,
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p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
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p->src_seg_id, p->dest_iosapic_intin,
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((u32 *) p)[2],
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((u32 *) p)[3]
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);
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}
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}
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#endif /* DEBUG_IOSAPIC_IRT */
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return num_entries;
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}
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void __init iosapic_init(void)
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{
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unsigned long cell = 0;
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DBG("iosapic_init()\n");
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#ifdef __LP64__
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if (is_pdc_pat()) {
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int status;
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struct pdc_pat_cell_num cell_info;
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status = pdc_pat_cell_get_number(&cell_info);
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if (status == PDC_OK) {
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cell = cell_info.cell_num;
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}
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}
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#endif
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/* get interrupt routing table for this cell */
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irt_num_entry = iosapic_load_irt(cell, &irt_cell);
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if (irt_num_entry == 0)
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irt_cell = NULL; /* old PDC w/o iosapic */
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}
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/*
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** Return the IRT entry in case we need to look something else up.
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*/
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static struct irt_entry *
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irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin)
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{
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struct irt_entry *i = irt_cell;
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int cnt; /* track how many entries we've looked at */
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u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1);
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DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin);
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for (cnt=0; cnt < irt_num_entry; cnt++, i++) {
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/*
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** Validate: entry_type, entry_length, interrupt_type
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**
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** Difference between validate vs compare is the former
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** should print debug info and is not expected to "fail"
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** on current platforms.
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*/
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if (i->entry_type != IRT_IOSAPIC_TYPE) {
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DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type);
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continue;
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}
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if (i->entry_length != IRT_IOSAPIC_LENGTH) {
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DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length);
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continue;
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}
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if (i->interrupt_type != IRT_VECTORED_INTR) {
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DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type);
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continue;
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}
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if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa))
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continue;
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if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno)
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continue;
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/*
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** Ignore: src_bus_id and rc_seg_id correlate with
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** iosapic_info->isi_hpa on HP platforms.
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** If needed, pass in "PFA" (aka config space addr)
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** instead of slot.
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*/
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/* Found it! */
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return i;
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}
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printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n",
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isi->isi_hpa, slot, intr_pin);
|
|
return NULL;
|
|
}
|
|
|
|
|
|
/*
|
|
** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges.
|
|
** Legacy PDC already does this translation for us and stores it in INTR_LINE.
|
|
**
|
|
** PAT PDC needs to basically do what legacy PDC does:
|
|
** o read PIN
|
|
** o adjust PIN in case device is "behind" a PPB
|
|
** (eg 4-port 100BT and SCSI/LAN "Combo Card")
|
|
** o convert slot/pin to I/O SAPIC input line.
|
|
**
|
|
** HP platforms only support:
|
|
** o one level of skewing for any number of PPBs
|
|
** o only support PCI-PCI Bridges.
|
|
*/
|
|
static struct irt_entry *
|
|
iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
|
|
{
|
|
u8 intr_pin, intr_slot;
|
|
|
|
pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin);
|
|
|
|
DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n",
|
|
pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin);
|
|
|
|
if (intr_pin == 0) {
|
|
/* The device does NOT support/use IRQ lines. */
|
|
return NULL;
|
|
}
|
|
|
|
/* Check if pcidev behind a PPB */
|
|
if (pcidev->bus->parent) {
|
|
/* Convert pcidev INTR_PIN into something we
|
|
** can lookup in the IRT.
|
|
*/
|
|
#ifdef PCI_BRIDGE_FUNCS
|
|
/*
|
|
** Proposal #1:
|
|
**
|
|
** call implementation specific translation function
|
|
** This is architecturally "cleaner". HP-UX doesn't
|
|
** support other secondary bus types (eg. E/ISA) directly.
|
|
** May be needed for other processor (eg IA64) architectures
|
|
** or by some ambitous soul who wants to watch TV.
|
|
*/
|
|
if (pci_bridge_funcs->xlate_intr_line) {
|
|
intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev);
|
|
}
|
|
#else /* PCI_BRIDGE_FUNCS */
|
|
struct pci_bus *p = pcidev->bus;
|
|
/*
|
|
** Proposal #2:
|
|
** The "pin" is skewed ((pin + dev - 1) % 4).
|
|
**
|
|
** This isn't very clean since I/O SAPIC must assume:
|
|
** - all platforms only have PCI busses.
|
|
** - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA)
|
|
** - IRQ routing is only skewed once regardless of
|
|
** the number of PPB's between iosapic and device.
|
|
** (Bit3 expansion chassis follows this rule)
|
|
**
|
|
** Advantage is it's really easy to implement.
|
|
*/
|
|
intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin);
|
|
#endif /* PCI_BRIDGE_FUNCS */
|
|
|
|
/*
|
|
* Locate the host slot of the PPB.
|
|
*/
|
|
while (p->parent->parent)
|
|
p = p->parent;
|
|
|
|
intr_slot = PCI_SLOT(p->self->devfn);
|
|
} else {
|
|
intr_slot = PCI_SLOT(pcidev->devfn);
|
|
}
|
|
DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
|
|
pcidev->bus->busn_res.start, intr_slot, intr_pin);
|
|
|
|
return irt_find_irqline(isi, intr_slot, intr_pin);
|
|
}
|
|
|
|
static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
|
|
{
|
|
struct iosapic_info *isp = vi->iosapic;
|
|
u8 idx = vi->irqline;
|
|
|
|
*dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx));
|
|
*dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx));
|
|
}
|
|
|
|
|
|
static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
|
|
{
|
|
struct iosapic_info *isp = vi->iosapic;
|
|
|
|
DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n",
|
|
vi->irqline, isp->isi_hpa, dp0, dp1);
|
|
|
|
iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
|
|
|
|
/* Read the window register to flush the writes down to HW */
|
|
dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW);
|
|
|
|
iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
|
|
|
|
/* Read the window register to flush the writes down to HW */
|
|
dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW);
|
|
}
|
|
|
|
/*
|
|
** set_irt prepares the data (dp0, dp1) according to the vector_info
|
|
** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC
|
|
** IRdT for the given "vector" (aka IRQ line).
|
|
*/
|
|
static void
|
|
iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
|
|
{
|
|
u32 mode = 0;
|
|
struct irt_entry *p = vi->irte;
|
|
|
|
if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO)
|
|
mode |= IOSAPIC_IRDT_PO_LOW;
|
|
|
|
if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG)
|
|
mode |= IOSAPIC_IRDT_LEVEL_TRIG;
|
|
|
|
/*
|
|
** IA64 REVISIT
|
|
** PA doesn't support EXTINT or LPRIO bits.
|
|
*/
|
|
|
|
*dp0 = mode | (u32) vi->txn_data;
|
|
|
|
/*
|
|
** Extracting id_eid isn't a real clean way of getting it.
|
|
** But the encoding is the same for both PA and IA64 platforms.
|
|
*/
|
|
if (is_pdc_pat()) {
|
|
/*
|
|
** PAT PDC just hands it to us "right".
|
|
** txn_addr comes from cpu_data[x].txn_addr.
|
|
*/
|
|
*dp1 = (u32) (vi->txn_addr);
|
|
} else {
|
|
/*
|
|
** eg if base_addr == 0xfffa0000),
|
|
** we want to get 0xa0ff0000.
|
|
**
|
|
** eid 0x0ff00000 -> 0x00ff0000
|
|
** id 0x000ff000 -> 0xff000000
|
|
*/
|
|
*dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) |
|
|
(((u32)vi->txn_addr & 0x000ff000) << 12);
|
|
}
|
|
DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1);
|
|
}
|
|
|
|
|
|
static void iosapic_mask_irq(struct irq_data *d)
|
|
{
|
|
unsigned long flags;
|
|
struct vector_info *vi = irq_data_get_irq_chip_data(d);
|
|
u32 d0, d1;
|
|
|
|
spin_lock_irqsave(&iosapic_lock, flags);
|
|
iosapic_rd_irt_entry(vi, &d0, &d1);
|
|
d0 |= IOSAPIC_IRDT_ENABLE;
|
|
iosapic_wr_irt_entry(vi, d0, d1);
|
|
spin_unlock_irqrestore(&iosapic_lock, flags);
|
|
}
|
|
|
|
static void iosapic_unmask_irq(struct irq_data *d)
|
|
{
|
|
struct vector_info *vi = irq_data_get_irq_chip_data(d);
|
|
u32 d0, d1;
|
|
|
|
/* data is initialized by fixup_irq */
|
|
WARN_ON(vi->txn_irq == 0);
|
|
|
|
iosapic_set_irt_data(vi, &d0, &d1);
|
|
iosapic_wr_irt_entry(vi, d0, d1);
|
|
|
|
#ifdef DEBUG_IOSAPIC_IRT
|
|
{
|
|
u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
|
|
printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
|
|
for ( ; t < vi->eoi_addr; t++)
|
|
printk(" %x", readl(t));
|
|
printk("\n");
|
|
}
|
|
|
|
printk("iosapic_enable_irq(): sel ");
|
|
{
|
|
struct iosapic_info *isp = vi->iosapic;
|
|
|
|
for (d0=0x10; d0<0x1e; d0++) {
|
|
d1 = iosapic_read(isp->addr, d0);
|
|
printk(" %x", d1);
|
|
}
|
|
}
|
|
printk("\n");
|
|
#endif
|
|
|
|
/*
|
|
* Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is
|
|
* asserted. IRQ generally should not be asserted when a driver
|
|
* enables their IRQ. It can lead to "interesting" race conditions
|
|
* in the driver initialization sequence.
|
|
*/
|
|
DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", d->irq,
|
|
vi->eoi_addr, vi->eoi_data);
|
|
iosapic_eoi(vi->eoi_addr, vi->eoi_data);
|
|
}
|
|
|
|
static void iosapic_eoi_irq(struct irq_data *d)
|
|
{
|
|
struct vector_info *vi = irq_data_get_irq_chip_data(d);
|
|
|
|
iosapic_eoi(vi->eoi_addr, vi->eoi_data);
|
|
cpu_eoi_irq(d);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
static int iosapic_set_affinity_irq(struct irq_data *d,
|
|
const struct cpumask *dest, bool force)
|
|
{
|
|
struct vector_info *vi = irq_data_get_irq_chip_data(d);
|
|
u32 d0, d1, dummy_d0;
|
|
unsigned long flags;
|
|
int dest_cpu;
|
|
|
|
dest_cpu = cpu_check_affinity(d, dest);
|
|
if (dest_cpu < 0)
|
|
return -1;
|
|
|
|
cpumask_copy(irq_data_get_affinity_mask(d), cpumask_of(dest_cpu));
|
|
vi->txn_addr = txn_affinity_addr(d->irq, dest_cpu);
|
|
|
|
spin_lock_irqsave(&iosapic_lock, flags);
|
|
/* d1 contains the destination CPU, so only want to set that
|
|
* entry */
|
|
iosapic_rd_irt_entry(vi, &d0, &d1);
|
|
iosapic_set_irt_data(vi, &dummy_d0, &d1);
|
|
iosapic_wr_irt_entry(vi, d0, d1);
|
|
spin_unlock_irqrestore(&iosapic_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct irq_chip iosapic_interrupt_type = {
|
|
.name = "IO-SAPIC-level",
|
|
.irq_unmask = iosapic_unmask_irq,
|
|
.irq_mask = iosapic_mask_irq,
|
|
.irq_ack = cpu_ack_irq,
|
|
.irq_eoi = iosapic_eoi_irq,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = iosapic_set_affinity_irq,
|
|
#endif
|
|
};
|
|
|
|
int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
|
|
{
|
|
struct iosapic_info *isi = isi_obj;
|
|
struct irt_entry *irte = NULL; /* only used if PAT PDC */
|
|
struct vector_info *vi;
|
|
int isi_line; /* line used by device */
|
|
|
|
if (!isi) {
|
|
printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n",
|
|
pci_name(pcidev));
|
|
return -1;
|
|
}
|
|
|
|
#ifdef CONFIG_SUPERIO
|
|
/*
|
|
* HACK ALERT! (non-compliant PCI device support)
|
|
*
|
|
* All SuckyIO interrupts are routed through the PIC's on function 1.
|
|
* But SuckyIO OHCI USB controller gets an IRT entry anyway because
|
|
* it advertises INT D for INT_PIN. Use that IRT entry to get the
|
|
* SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*).
|
|
*/
|
|
if (is_superio_device(pcidev)) {
|
|
/* We must call superio_fixup_irq() to register the pdev */
|
|
pcidev->irq = superio_fixup_irq(pcidev);
|
|
|
|
/* Don't return if need to program the IOSAPIC's IRT... */
|
|
if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN)
|
|
return pcidev->irq;
|
|
}
|
|
#endif /* CONFIG_SUPERIO */
|
|
|
|
/* lookup IRT entry for isi/slot/pin set */
|
|
irte = iosapic_xlate_pin(isi, pcidev);
|
|
if (!irte) {
|
|
printk("iosapic: no IRTE for %s (IRQ not connected?)\n",
|
|
pci_name(pcidev));
|
|
return -1;
|
|
}
|
|
DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n",
|
|
irte,
|
|
irte->entry_type,
|
|
irte->entry_length,
|
|
irte->polarity_trigger,
|
|
irte->src_bus_irq_devno,
|
|
irte->src_bus_id,
|
|
irte->src_seg_id,
|
|
irte->dest_iosapic_intin,
|
|
(u32) irte->dest_iosapic_addr);
|
|
isi_line = irte->dest_iosapic_intin;
|
|
|
|
/* get vector info for this input line */
|
|
vi = isi->isi_vector + isi_line;
|
|
DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi);
|
|
|
|
/* If this IRQ line has already been setup, skip it */
|
|
if (vi->irte)
|
|
goto out;
|
|
|
|
vi->irte = irte;
|
|
|
|
/*
|
|
* Allocate processor IRQ
|
|
*
|
|
* XXX/FIXME The txn_alloc_irq() code and related code should be
|
|
* moved to enable_irq(). That way we only allocate processor IRQ
|
|
* bits for devices that actually have drivers claiming them.
|
|
* Right now we assign an IRQ to every PCI device present,
|
|
* regardless of whether it's used or not.
|
|
*/
|
|
vi->txn_irq = txn_alloc_irq(8);
|
|
|
|
if (vi->txn_irq < 0)
|
|
panic("I/O sapic: couldn't get TXN IRQ\n");
|
|
|
|
/* enable_irq() will use txn_* to program IRdT */
|
|
vi->txn_addr = txn_alloc_addr(vi->txn_irq);
|
|
vi->txn_data = txn_alloc_data(vi->txn_irq);
|
|
|
|
vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
|
|
vi->eoi_data = cpu_to_le32(vi->txn_data);
|
|
|
|
cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
|
|
|
|
out:
|
|
pcidev->irq = vi->txn_irq;
|
|
|
|
DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
|
|
PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn),
|
|
pcidev->vendor, pcidev->device, isi_line, pcidev->irq);
|
|
|
|
return pcidev->irq;
|
|
}
|
|
|
|
static struct iosapic_info *iosapic_list;
|
|
|
|
#ifdef CONFIG_64BIT
|
|
int iosapic_serial_irq(struct parisc_device *dev)
|
|
{
|
|
struct iosapic_info *isi;
|
|
struct irt_entry *irte;
|
|
struct vector_info *vi;
|
|
int cnt;
|
|
int intin;
|
|
|
|
intin = (dev->mod_info >> 24) & 15;
|
|
|
|
/* lookup IRT entry for isi/slot/pin set */
|
|
for (cnt = 0; cnt < irt_num_entry; cnt++) {
|
|
irte = &irt_cell[cnt];
|
|
if (COMPARE_IRTE_ADDR(irte, dev->mod0) &&
|
|
irte->dest_iosapic_intin == intin)
|
|
break;
|
|
}
|
|
if (cnt >= irt_num_entry)
|
|
return 0; /* no irq found, force polling */
|
|
|
|
DBG_IRT("iosapic_serial_irq(): irte %p %x %x %x %x %x %x %x %x\n",
|
|
irte,
|
|
irte->entry_type,
|
|
irte->entry_length,
|
|
irte->polarity_trigger,
|
|
irte->src_bus_irq_devno,
|
|
irte->src_bus_id,
|
|
irte->src_seg_id,
|
|
irte->dest_iosapic_intin,
|
|
(u32) irte->dest_iosapic_addr);
|
|
|
|
/* search for iosapic */
|
|
for (isi = iosapic_list; isi; isi = isi->isi_next)
|
|
if (isi->isi_hpa == dev->mod0)
|
|
break;
|
|
if (!isi)
|
|
return 0; /* no iosapic found, force polling */
|
|
|
|
/* get vector info for this input line */
|
|
vi = isi->isi_vector + intin;
|
|
DBG_IRT("iosapic_serial_irq: line %d vi 0x%p\n", iosapic_intin, vi);
|
|
|
|
/* If this IRQ line has already been setup, skip it */
|
|
if (vi->irte)
|
|
goto out;
|
|
|
|
vi->irte = irte;
|
|
|
|
/*
|
|
* Allocate processor IRQ
|
|
*
|
|
* XXX/FIXME The txn_alloc_irq() code and related code should be
|
|
* moved to enable_irq(). That way we only allocate processor IRQ
|
|
* bits for devices that actually have drivers claiming them.
|
|
* Right now we assign an IRQ to every PCI device present,
|
|
* regardless of whether it's used or not.
|
|
*/
|
|
vi->txn_irq = txn_alloc_irq(8);
|
|
|
|
if (vi->txn_irq < 0)
|
|
panic("I/O sapic: couldn't get TXN IRQ\n");
|
|
|
|
/* enable_irq() will use txn_* to program IRdT */
|
|
vi->txn_addr = txn_alloc_addr(vi->txn_irq);
|
|
vi->txn_data = txn_alloc_data(vi->txn_irq);
|
|
|
|
vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
|
|
vi->eoi_data = cpu_to_le32(vi->txn_data);
|
|
|
|
cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
|
|
|
|
out:
|
|
|
|
return vi->txn_irq;
|
|
}
|
|
#endif
|
|
|
|
|
|
/*
|
|
** squirrel away the I/O Sapic Version
|
|
*/
|
|
static unsigned int
|
|
iosapic_rd_version(struct iosapic_info *isi)
|
|
{
|
|
return iosapic_read(isi->addr, IOSAPIC_REG_VERSION);
|
|
}
|
|
|
|
|
|
/*
|
|
** iosapic_register() is called by "drivers" with an integrated I/O SAPIC.
|
|
** Caller must be certain they have an I/O SAPIC and know its MMIO address.
|
|
**
|
|
** o allocate iosapic_info and add it to the list
|
|
** o read iosapic version and squirrel that away
|
|
** o read size of IRdT.
|
|
** o allocate and initialize isi_vector[]
|
|
** o allocate irq region
|
|
*/
|
|
void *iosapic_register(unsigned long hpa)
|
|
{
|
|
struct iosapic_info *isi = NULL;
|
|
struct irt_entry *irte = irt_cell;
|
|
struct vector_info *vip;
|
|
int cnt; /* track how many entries we've looked at */
|
|
|
|
/*
|
|
* Astro based platforms can only support PCI OLARD if they implement
|
|
* PAT PDC. Legacy PDC omits LBAs with no PCI devices from the IRT.
|
|
* Search the IRT and ignore iosapic's which aren't in the IRT.
|
|
*/
|
|
for (cnt=0; cnt < irt_num_entry; cnt++, irte++) {
|
|
WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type);
|
|
if (COMPARE_IRTE_ADDR(irte, hpa))
|
|
break;
|
|
}
|
|
|
|
if (cnt >= irt_num_entry) {
|
|
DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa);
|
|
return NULL;
|
|
}
|
|
|
|
isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL);
|
|
if (!isi) {
|
|
BUG();
|
|
return NULL;
|
|
}
|
|
|
|
isi->addr = ioremap_nocache(hpa, 4096);
|
|
isi->isi_hpa = hpa;
|
|
isi->isi_version = iosapic_rd_version(isi);
|
|
isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1;
|
|
|
|
vip = isi->isi_vector = kcalloc(isi->isi_num_vectors,
|
|
sizeof(struct vector_info), GFP_KERNEL);
|
|
if (vip == NULL) {
|
|
kfree(isi);
|
|
return NULL;
|
|
}
|
|
|
|
for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) {
|
|
vip->irqline = (unsigned char) cnt;
|
|
vip->iosapic = isi;
|
|
}
|
|
isi->isi_next = iosapic_list;
|
|
iosapic_list = isi;
|
|
return isi;
|
|
}
|
|
|
|
|
|
#ifdef DEBUG_IOSAPIC
|
|
|
|
static void
|
|
iosapic_prt_irt(void *irt, long num_entry)
|
|
{
|
|
unsigned int i, *irp = (unsigned int *) irt;
|
|
|
|
|
|
printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry);
|
|
|
|
for (i=0; i<num_entry; i++, irp += 4) {
|
|
printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n",
|
|
irp, i, irp[0], irp[1], irp[2], irp[3]);
|
|
}
|
|
}
|
|
|
|
|
|
static void
|
|
iosapic_prt_vi(struct vector_info *vi)
|
|
{
|
|
printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi);
|
|
printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status);
|
|
printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq);
|
|
printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr);
|
|
printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data);
|
|
printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr);
|
|
printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data);
|
|
}
|
|
|
|
|
|
static void
|
|
iosapic_prt_isi(struct iosapic_info *isi)
|
|
{
|
|
printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi);
|
|
printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa);
|
|
printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status);
|
|
printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version);
|
|
printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector);
|
|
}
|
|
#endif /* DEBUG_IOSAPIC */
|