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16c4ea7501
switch to new lpcg clock binding Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
62 lines
1.1 KiB
Plaintext
62 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2020 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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&lsio_gpio0 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio1 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio2 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio3 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio4 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio5 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio6 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_gpio7 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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};
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&lsio_mu0 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu1 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu2 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu3 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu4 {
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compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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};
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&lsio_mu13 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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};
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