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1bd187de53
Since we have a native 8250 driver carrying the Intel MID serial devices the specific support is not needed anymore. This patch removes it for Intel MID. Note that the console device name is changed from ttyMFDx to ttySx. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
152 lines
4.3 KiB
C
152 lines
4.3 KiB
C
/*
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* intel-mid.h: Intel MID specific setup code
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*
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* (C) Copyright 2009 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _ASM_X86_INTEL_MID_H
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#define _ASM_X86_INTEL_MID_H
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#include <linux/sfi.h>
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#include <linux/platform_device.h>
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extern int intel_mid_pci_init(void);
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extern int get_gpio_by_name(const char *name);
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extern void intel_scu_device_register(struct platform_device *pdev);
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extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
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extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
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extern int sfi_mrtc_num;
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extern struct sfi_rtc_table_entry sfi_mrtc_array[];
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/*
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* Here defines the array of devices platform data that IAFW would export
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* through SFI "DEVS" table, we use name and type to match the device and
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* its platform data.
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*/
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struct devs_id {
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char name[SFI_NAME_LEN + 1];
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u8 type;
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u8 delay;
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void *(*get_platform_data)(void *info);
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/* Custom handler for devices */
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void (*device_handler)(struct sfi_device_table_entry *pentry,
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struct devs_id *dev);
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};
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#define sfi_device(i) \
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static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
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__attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum intel_mid_cpu_type {
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/* 1 was Moorestown */
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INTEL_MID_CPU_CHIP_PENWELL = 2,
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INTEL_MID_CPU_CHIP_CLOVERVIEW,
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INTEL_MID_CPU_CHIP_TANGIER,
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};
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extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
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/**
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* struct intel_mid_ops - Interface between intel-mid & sub archs
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* @arch_setup: arch_setup function to re-initialize platform
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* structures (x86_init, x86_platform_init)
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*
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* This structure can be extended if any new interface is required
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* between intel-mid & its sub arch files.
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*/
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struct intel_mid_ops {
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void (*arch_setup)(void);
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};
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/* Helper API's for INTEL_MID_OPS_INIT */
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#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
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[cpuid] = get_##cpuname##_ops
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/* Maximum number of CPU ops */
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#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
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/*
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* For every new cpu addition, a weak get_<cpuname>_ops() function needs be
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* declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
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*/
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#define INTEL_MID_OPS_INIT {\
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DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
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DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
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DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
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};
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#ifdef CONFIG_X86_INTEL_MID
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static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
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{
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return __intel_mid_cpu_chip;
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}
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static inline bool intel_mid_has_msic(void)
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{
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return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
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}
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#else /* !CONFIG_X86_INTEL_MID */
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#define intel_mid_identify_cpu() (0)
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#define intel_mid_has_msic() (0)
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#endif /* !CONFIG_X86_INTEL_MID */
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enum intel_mid_timer_options {
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INTEL_MID_TIMER_DEFAULT,
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INTEL_MID_TIMER_APBT_ONLY,
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INTEL_MID_TIMER_LAPIC_APBT,
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};
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extern enum intel_mid_timer_options intel_mid_timer_options;
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/*
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* Penwell uses spread spectrum clock, so the freq number is not exactly
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* the same as reported by MSR based on SDM.
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*/
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#define FSB_FREQ_83SKU 83200
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#define FSB_FREQ_100SKU 99840
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#define FSB_FREQ_133SKU 133000
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#define FSB_FREQ_167SKU 167000
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#define FSB_FREQ_200SKU 200000
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#define FSB_FREQ_267SKU 267000
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#define FSB_FREQ_333SKU 333000
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#define FSB_FREQ_400SKU 400000
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/* Bus Select SoC Fuse value */
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#define BSEL_SOC_FUSE_MASK 0x7
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#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
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#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
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#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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extern void intel_scu_devices_create(void);
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extern void intel_scu_devices_destroy(void);
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/* VRTC timer */
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#define MRST_VRTC_MAP_SZ (1024)
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/*#define MRST_VRTC_PGOFFSET (0xc00) */
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extern void intel_mid_rtc_init(void);
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/* the offset for the mapping of global gpio pin to irq */
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#define INTEL_MID_IRQ_OFFSET 0x100
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#endif /* _ASM_X86_INTEL_MID_H */
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