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faef87723a
The MIPS bmips platform needs a global flush when transferring ownership back to the CPU. Add a hook for that to the dma-noncoherent implementation. Signed-off-by: Christoph Hellwig <hch@lst.de> Patchwork: https://patchwork.linux-mips.org/patch/19549/ Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: David Daney <david.daney@cavium.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de> Cc: Huacai Chen <chenhc@lemote.com> Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Christoph Hellwig.
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*
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* DMA operations that map physical memory directly without providing cache
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* coherence.
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/dma-direct.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/scatterlist.h>
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static void dma_noncoherent_sync_single_for_device(struct device *dev,
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dma_addr_t addr, size_t size, enum dma_data_direction dir)
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{
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arch_sync_dma_for_device(dev, dma_to_phys(dev, addr), size, dir);
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}
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static void dma_noncoherent_sync_sg_for_device(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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arch_sync_dma_for_device(dev, sg_phys(sg), sg->length, dir);
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}
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static dma_addr_t dma_noncoherent_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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dma_addr_t addr;
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addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
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if (!dma_mapping_error(dev, addr) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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arch_sync_dma_for_device(dev, page_to_phys(page) + offset,
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size, dir);
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return addr;
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}
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static int dma_noncoherent_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir, unsigned long attrs)
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{
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nents = dma_direct_map_sg(dev, sgl, nents, dir, attrs);
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if (nents > 0 && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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dma_noncoherent_sync_sg_for_device(dev, sgl, nents, dir);
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return nents;
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}
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
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static void dma_noncoherent_sync_single_for_cpu(struct device *dev,
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dma_addr_t addr, size_t size, enum dma_data_direction dir)
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{
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arch_sync_dma_for_cpu(dev, dma_to_phys(dev, addr), size, dir);
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arch_sync_dma_for_cpu_all(dev);
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}
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static void dma_noncoherent_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
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arch_sync_dma_for_cpu_all(dev);
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}
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static void dma_noncoherent_unmap_page(struct device *dev, dma_addr_t addr,
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size_t size, enum dma_data_direction dir, unsigned long attrs)
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{
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if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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dma_noncoherent_sync_single_for_cpu(dev, addr, size, dir);
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}
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static void dma_noncoherent_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir, unsigned long attrs)
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{
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if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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dma_noncoherent_sync_sg_for_cpu(dev, sgl, nents, dir);
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}
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#endif
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const struct dma_map_ops dma_noncoherent_ops = {
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.alloc = arch_dma_alloc,
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.free = arch_dma_free,
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.mmap = arch_dma_mmap,
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.sync_single_for_device = dma_noncoherent_sync_single_for_device,
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.sync_sg_for_device = dma_noncoherent_sync_sg_for_device,
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.map_page = dma_noncoherent_map_page,
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.map_sg = dma_noncoherent_map_sg,
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
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.sync_single_for_cpu = dma_noncoherent_sync_single_for_cpu,
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.sync_sg_for_cpu = dma_noncoherent_sync_sg_for_cpu,
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.unmap_page = dma_noncoherent_unmap_page,
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.unmap_sg = dma_noncoherent_unmap_sg,
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#endif
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.dma_supported = dma_direct_supported,
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.mapping_error = dma_direct_mapping_error,
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.cache_sync = arch_dma_cache_sync,
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};
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EXPORT_SYMBOL(dma_noncoherent_ops);
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