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3b5e748615
Add all supported clocks exported from every susbystem found on MT7629 SoC. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
204 lines
5.6 KiB
C
204 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_CLK_MT7629_H
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#define _DT_BINDINGS_CLK_MT7629_H
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/* TOPCKGEN */
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#define CLK_TOP_TO_U2_PHY 0
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#define CLK_TOP_TO_U2_PHY_1P 1
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#define CLK_TOP_PCIE0_PIPE_EN 2
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#define CLK_TOP_PCIE1_PIPE_EN 3
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#define CLK_TOP_SSUSB_TX250M 4
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#define CLK_TOP_SSUSB_EQ_RX250M 5
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#define CLK_TOP_SSUSB_CDR_REF 6
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#define CLK_TOP_SSUSB_CDR_FB 7
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#define CLK_TOP_SATA_ASIC 8
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#define CLK_TOP_SATA_RBC 9
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#define CLK_TOP_TO_USB3_SYS 10
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#define CLK_TOP_P1_1MHZ 11
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#define CLK_TOP_4MHZ 12
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#define CLK_TOP_P0_1MHZ 13
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#define CLK_TOP_ETH_500M 14
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#define CLK_TOP_TXCLK_SRC_PRE 15
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#define CLK_TOP_RTC 16
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#define CLK_TOP_PWM_QTR_26M 17
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#define CLK_TOP_CPUM_TCK_IN 18
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#define CLK_TOP_TO_USB3_DA_TOP 19
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#define CLK_TOP_MEMPLL 20
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#define CLK_TOP_DMPLL 21
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#define CLK_TOP_DMPLL_D4 22
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#define CLK_TOP_DMPLL_D8 23
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#define CLK_TOP_SYSPLL_D2 24
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#define CLK_TOP_SYSPLL1_D2 25
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#define CLK_TOP_SYSPLL1_D4 26
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#define CLK_TOP_SYSPLL1_D8 27
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#define CLK_TOP_SYSPLL1_D16 28
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#define CLK_TOP_SYSPLL2_D2 29
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#define CLK_TOP_SYSPLL2_D4 30
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#define CLK_TOP_SYSPLL2_D8 31
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#define CLK_TOP_SYSPLL_D5 32
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#define CLK_TOP_SYSPLL3_D2 33
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#define CLK_TOP_SYSPLL3_D4 34
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#define CLK_TOP_SYSPLL_D7 35
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#define CLK_TOP_SYSPLL4_D2 36
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#define CLK_TOP_SYSPLL4_D4 37
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#define CLK_TOP_SYSPLL4_D16 38
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#define CLK_TOP_UNIVPLL 39
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#define CLK_TOP_UNIVPLL1_D2 40
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#define CLK_TOP_UNIVPLL1_D4 41
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#define CLK_TOP_UNIVPLL1_D8 42
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#define CLK_TOP_UNIVPLL_D3 43
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#define CLK_TOP_UNIVPLL2_D2 44
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#define CLK_TOP_UNIVPLL2_D4 45
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#define CLK_TOP_UNIVPLL2_D8 46
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#define CLK_TOP_UNIVPLL2_D16 47
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#define CLK_TOP_UNIVPLL_D5 48
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#define CLK_TOP_UNIVPLL3_D2 49
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#define CLK_TOP_UNIVPLL3_D4 50
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#define CLK_TOP_UNIVPLL3_D16 51
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#define CLK_TOP_UNIVPLL_D7 52
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#define CLK_TOP_UNIVPLL_D80_D4 53
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#define CLK_TOP_UNIV48M 54
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#define CLK_TOP_SGMIIPLL_D2 55
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#define CLK_TOP_CLKXTAL_D4 56
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#define CLK_TOP_HD_FAXI 57
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#define CLK_TOP_FAXI 58
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#define CLK_TOP_F_FAUD_INTBUS 59
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#define CLK_TOP_AP2WBHIF_HCLK 60
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#define CLK_TOP_10M_INFRAO 61
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#define CLK_TOP_MSDC30_1 62
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#define CLK_TOP_SPI 63
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#define CLK_TOP_SF 64
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#define CLK_TOP_FLASH 65
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#define CLK_TOP_TO_USB3_REF 66
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#define CLK_TOP_TO_USB3_MCU 67
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#define CLK_TOP_TO_USB3_DMA 68
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#define CLK_TOP_FROM_TOP_AHB 69
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#define CLK_TOP_FROM_TOP_AXI 70
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#define CLK_TOP_PCIE1_MAC_EN 71
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#define CLK_TOP_PCIE0_MAC_EN 72
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#define CLK_TOP_AXI_SEL 73
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#define CLK_TOP_MEM_SEL 74
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#define CLK_TOP_DDRPHYCFG_SEL 75
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#define CLK_TOP_ETH_SEL 76
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#define CLK_TOP_PWM_SEL 77
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#define CLK_TOP_F10M_REF_SEL 78
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#define CLK_TOP_NFI_INFRA_SEL 79
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#define CLK_TOP_FLASH_SEL 80
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#define CLK_TOP_UART_SEL 81
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#define CLK_TOP_SPI0_SEL 82
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#define CLK_TOP_SPI1_SEL 83
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#define CLK_TOP_MSDC50_0_SEL 84
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#define CLK_TOP_MSDC30_0_SEL 85
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#define CLK_TOP_MSDC30_1_SEL 86
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#define CLK_TOP_AP2WBMCU_SEL 87
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#define CLK_TOP_AP2WBHIF_SEL 88
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#define CLK_TOP_AUDIO_SEL 89
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#define CLK_TOP_AUD_INTBUS_SEL 90
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#define CLK_TOP_PMICSPI_SEL 91
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#define CLK_TOP_SCP_SEL 92
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#define CLK_TOP_ATB_SEL 93
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#define CLK_TOP_HIF_SEL 94
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#define CLK_TOP_SATA_SEL 95
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#define CLK_TOP_U2_SEL 96
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#define CLK_TOP_AUD1_SEL 97
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#define CLK_TOP_AUD2_SEL 98
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#define CLK_TOP_IRRX_SEL 99
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#define CLK_TOP_IRTX_SEL 100
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#define CLK_TOP_SATA_MCU_SEL 101
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#define CLK_TOP_PCIE0_MCU_SEL 102
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#define CLK_TOP_PCIE1_MCU_SEL 103
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#define CLK_TOP_SSUSB_MCU_SEL 104
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#define CLK_TOP_CRYPTO_SEL 105
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#define CLK_TOP_SGMII_REF_1_SEL 106
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#define CLK_TOP_10M_SEL 107
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#define CLK_TOP_NR_CLK 108
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/* INFRACFG */
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#define CLK_INFRA_MUX1_SEL 0
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#define CLK_INFRA_DBGCLK_PD 1
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#define CLK_INFRA_TRNG_PD 2
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#define CLK_INFRA_DEVAPC_PD 3
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#define CLK_INFRA_APXGPT_PD 4
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#define CLK_INFRA_SEJ_PD 5
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#define CLK_INFRA_NR_CLK 6
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/* PERICFG */
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#define CLK_PERIBUS_SEL 0
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#define CLK_PERI_PWM1_PD 1
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#define CLK_PERI_PWM2_PD 2
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#define CLK_PERI_PWM3_PD 3
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#define CLK_PERI_PWM4_PD 4
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#define CLK_PERI_PWM5_PD 5
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#define CLK_PERI_PWM6_PD 6
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#define CLK_PERI_PWM7_PD 7
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#define CLK_PERI_PWM_PD 8
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#define CLK_PERI_AP_DMA_PD 9
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#define CLK_PERI_MSDC30_1_PD 10
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#define CLK_PERI_UART0_PD 11
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#define CLK_PERI_UART1_PD 12
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#define CLK_PERI_UART2_PD 13
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#define CLK_PERI_UART3_PD 14
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#define CLK_PERI_BTIF_PD 15
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#define CLK_PERI_I2C0_PD 16
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#define CLK_PERI_SPI0_PD 17
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#define CLK_PERI_SNFI_PD 18
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#define CLK_PERI_NFI_PD 19
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#define CLK_PERI_NFIECC_PD 20
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#define CLK_PERI_FLASH_PD 21
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#define CLK_PERI_NR_CLK 22
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIV2PLL 2
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#define CLK_APMIXED_ETH1PLL 3
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#define CLK_APMIXED_ETH2PLL 4
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#define CLK_APMIXED_SGMIPLL 5
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#define CLK_APMIXED_MAIN_CORE_EN 6
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#define CLK_APMIXED_NR_CLK 7
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/* SSUSBSYS */
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#define CLK_SSUSB_U2_PHY_1P_EN 0
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#define CLK_SSUSB_U2_PHY_EN 1
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#define CLK_SSUSB_REF_EN 2
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#define CLK_SSUSB_SYS_EN 3
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#define CLK_SSUSB_MCU_EN 4
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#define CLK_SSUSB_DMA_EN 5
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#define CLK_SSUSB_NR_CLK 6
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/* PCIESYS */
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#define CLK_PCIE_P1_AUX_EN 0
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#define CLK_PCIE_P1_OBFF_EN 1
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#define CLK_PCIE_P1_AHB_EN 2
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#define CLK_PCIE_P1_AXI_EN 3
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#define CLK_PCIE_P1_MAC_EN 4
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#define CLK_PCIE_P1_PIPE_EN 5
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#define CLK_PCIE_P0_AUX_EN 6
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#define CLK_PCIE_P0_OBFF_EN 7
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#define CLK_PCIE_P0_AHB_EN 8
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#define CLK_PCIE_P0_AXI_EN 9
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#define CLK_PCIE_P0_MAC_EN 10
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#define CLK_PCIE_P0_PIPE_EN 11
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#define CLK_PCIE_NR_CLK 12
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/* ETHSYS */
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#define CLK_ETH_FE_EN 0
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#define CLK_ETH_GP2_EN 1
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#define CLK_ETH_GP1_EN 2
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#define CLK_ETH_GP0_EN 3
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#define CLK_ETH_ESW_EN 4
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#define CLK_ETH_NR_CLK 5
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/* SGMIISYS */
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#define CLK_SGMII_TX_EN 0
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#define CLK_SGMII_RX_EN 1
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#define CLK_SGMII_CDR_REF 2
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#define CLK_SGMII_CDR_FB 3
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#define CLK_SGMII_NR_CLK 4
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#endif /* _DT_BINDINGS_CLK_MT7629_H */
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