David Daney 87161ccdc6 MIPS: Octeon: Fix broken interrupt controller code. ... Since 3.6.0-rc1, We are getting many messages like: WARNING: at kernel/irq/irqdomain.c:444 irq_domain_associate_many+0x23c/0x260() Modules linked in: Call Trace: [<ffffffff814cb698>] dump_stack+0x8/0x34 [<ffffffff81133d00>] warn_slowpath_common+0x78/0xa8 [<ffffffff81187e44>] irq_domain_associate_many+0x23c/0x260 [<ffffffff81187f38>] irq_create_mapping+0xd0/0x220 [<ffffffff81188104>] irq_create_of_mapping+0x7c/0x158 [<ffffffff813e5f08>] irq_of_parse_and_map+0x28/0x40 . . . Both the CIU and GPIO interrupt domains were somewhat screwed up. For the CIU domain, we need to call irq_domain_associate() for each of the preassigned irq numbers. For the GPIO domain, we were applying the register bit offset in octeon_irq_gpio_xlat, but it should be done in octeon_irq_gpio_map instead. Also: Reserve all 8 'core' irqs for the 'core' irq_chip so that they don't get used by the other domains. Remove unused OCTEON_IRQ_* symbols. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4190/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2012-08-17 10:57:26 +02:00
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cpu-feature-overrides.h	MIPS: Octeon: Enable C0_UserLocal probing.	2011-09-24 01:44:41 +02:00
dma-coherence.h	MIPS: Octeon: Rewrite DMA mapping functions.	2010-10-29 19:08:32 +01:00
irq.h	MIPS: Octeon: Fix broken interrupt controller code.	2012-08-17 10:57:26 +02:00
kernel-entry-init.h	Octeon: Fix interrupt irq settings for performance counters.	2011-05-19 09:55:49 +01:00
war.h	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	2009-01-11 09:57:21 +00:00