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56fbeefe36
Add support for 148.5MHz clock for HDMI PLL Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
441 lines
11 KiB
C
441 lines
11 KiB
C
/*
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* Synopsys HSDK SDP Generic PLL clock driver
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*
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* Copyright (C) 2017 Synopsys
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
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#define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
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#define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
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#define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
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#define CGU_PLL_CTRL_ODIV_SHIFT 2
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#define CGU_PLL_CTRL_IDIV_SHIFT 4
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#define CGU_PLL_CTRL_FBDIV_SHIFT 9
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#define CGU_PLL_CTRL_BAND_SHIFT 20
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#define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
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#define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
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#define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
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#define CGU_PLL_CTRL_PD BIT(0)
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#define CGU_PLL_CTRL_BYPASS BIT(1)
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#define CGU_PLL_STATUS_LOCK BIT(0)
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#define CGU_PLL_STATUS_ERR BIT(1)
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#define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
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#define CGU_PLL_SOURCE_MAX 1
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#define CORE_IF_CLK_THRESHOLD_HZ 500000000
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#define CREG_CORE_IF_CLK_DIV_1 0x0
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#define CREG_CORE_IF_CLK_DIV_2 0x1
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struct hsdk_pll_cfg {
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u32 rate;
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u32 idiv;
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u32 fbdiv;
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u32 odiv;
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u32 band;
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u32 bypass;
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};
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static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
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{ 100000000, 0, 11, 3, 0, 0 },
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{ 133000000, 0, 15, 3, 0, 0 },
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{ 200000000, 1, 47, 3, 0, 0 },
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{ 233000000, 1, 27, 2, 0, 0 },
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{ 300000000, 1, 35, 2, 0, 0 },
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{ 333000000, 1, 39, 2, 0, 0 },
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{ 400000000, 1, 47, 2, 0, 0 },
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{ 500000000, 0, 14, 1, 0, 0 },
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{ 600000000, 0, 17, 1, 0, 0 },
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{ 700000000, 0, 20, 1, 0, 0 },
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{ 800000000, 0, 23, 1, 0, 0 },
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{ 900000000, 1, 26, 0, 0, 0 },
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{ 1000000000, 1, 29, 0, 0, 0 },
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{ 1100000000, 1, 32, 0, 0, 0 },
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{ 1200000000, 1, 35, 0, 0, 0 },
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{ 1300000000, 1, 38, 0, 0, 0 },
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{ 1400000000, 1, 41, 0, 0, 0 },
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{ 1500000000, 1, 44, 0, 0, 0 },
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{ 1600000000, 1, 47, 0, 0, 0 },
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{}
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};
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static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
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{ 27000000, 0, 0, 0, 0, 1 },
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{ 148500000, 0, 21, 3, 0, 0 },
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{ 297000000, 0, 21, 2, 0, 0 },
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{ 540000000, 0, 19, 1, 0, 0 },
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{ 594000000, 0, 21, 1, 0, 0 },
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{}
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};
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struct hsdk_pll_clk {
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struct clk_hw hw;
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void __iomem *regs;
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void __iomem *spec_regs;
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const struct hsdk_pll_devdata *pll_devdata;
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struct device *dev;
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};
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struct hsdk_pll_devdata {
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const struct hsdk_pll_cfg *pll_cfg;
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int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
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const struct hsdk_pll_cfg *cfg);
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};
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static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
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const struct hsdk_pll_cfg *);
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static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
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const struct hsdk_pll_cfg *);
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static const struct hsdk_pll_devdata core_pll_devdata = {
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.pll_cfg = asdt_pll_cfg,
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.update_rate = hsdk_pll_core_update_rate,
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};
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static const struct hsdk_pll_devdata sdt_pll_devdata = {
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.pll_cfg = asdt_pll_cfg,
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.update_rate = hsdk_pll_comm_update_rate,
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};
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static const struct hsdk_pll_devdata hdmi_pll_devdata = {
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.pll_cfg = hdmi_pll_cfg,
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.update_rate = hsdk_pll_comm_update_rate,
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};
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static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
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{
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iowrite32(val, clk->regs + reg);
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}
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static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
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{
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return ioread32(clk->regs + reg);
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}
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static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
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const struct hsdk_pll_cfg *cfg)
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{
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u32 val = 0;
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if (cfg->bypass) {
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val = hsdk_pll_read(clk, CGU_PLL_CTRL);
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val |= CGU_PLL_CTRL_BYPASS;
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} else {
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/* Powerdown and Bypass bits should be cleared */
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val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
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val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
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val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
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val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
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}
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dev_dbg(clk->dev, "write configuration: %#x\n", val);
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hsdk_pll_write(clk, CGU_PLL_CTRL, val);
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}
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static inline bool hsdk_pll_is_locked(struct hsdk_pll_clk *clk)
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{
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return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
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}
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static inline bool hsdk_pll_is_err(struct hsdk_pll_clk *clk)
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{
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return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
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}
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static inline struct hsdk_pll_clk *to_hsdk_pll_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct hsdk_pll_clk, hw);
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}
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static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 val;
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u64 rate;
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u32 idiv, fbdiv, odiv;
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struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
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val = hsdk_pll_read(clk, CGU_PLL_CTRL);
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dev_dbg(clk->dev, "current configuration: %#x\n", val);
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/* Check if PLL is bypassed */
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if (val & CGU_PLL_CTRL_BYPASS)
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return parent_rate;
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/* Check if PLL is disabled */
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if (val & CGU_PLL_CTRL_PD)
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return 0;
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/* input divider = reg.idiv + 1 */
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idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
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/* fb divider = 2*(reg.fbdiv + 1) */
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fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
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/* output divider = 2^(reg.odiv) */
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odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
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rate = (u64)parent_rate * fbdiv;
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do_div(rate, idiv * odiv);
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return rate;
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}
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static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int i;
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unsigned long best_rate;
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struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
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const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
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if (pll_cfg[0].rate == 0)
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return -EINVAL;
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best_rate = pll_cfg[0].rate;
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for (i = 1; pll_cfg[i].rate != 0; i++) {
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if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
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best_rate = pll_cfg[i].rate;
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}
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dev_dbg(clk->dev, "chosen best rate: %lu\n", best_rate);
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return best_rate;
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}
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static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk,
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unsigned long rate,
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const struct hsdk_pll_cfg *cfg)
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{
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hsdk_pll_set_cfg(clk, cfg);
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/*
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* Wait until CGU relocks and check error status.
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* If after timeout CGU is unlocked yet return error.
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*/
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udelay(HSDK_PLL_MAX_LOCK_TIME);
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if (!hsdk_pll_is_locked(clk))
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return -ETIMEDOUT;
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if (hsdk_pll_is_err(clk))
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return -EINVAL;
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return 0;
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}
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static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
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unsigned long rate,
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const struct hsdk_pll_cfg *cfg)
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{
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/*
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* When core clock exceeds 500MHz, the divider for the interface
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* clock must be programmed to div-by-2.
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*/
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if (rate > CORE_IF_CLK_THRESHOLD_HZ)
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iowrite32(CREG_CORE_IF_CLK_DIV_2, clk->spec_regs);
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hsdk_pll_set_cfg(clk, cfg);
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/*
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* Wait until CGU relocks and check error status.
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* If after timeout CGU is unlocked yet return error.
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*/
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udelay(HSDK_PLL_MAX_LOCK_TIME);
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if (!hsdk_pll_is_locked(clk))
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return -ETIMEDOUT;
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if (hsdk_pll_is_err(clk))
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return -EINVAL;
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/*
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* Program divider to div-by-1 if we succesfuly set core clock below
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* 500MHz threshold.
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*/
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if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
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iowrite32(CREG_CORE_IF_CLK_DIV_1, clk->spec_regs);
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return 0;
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}
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static int hsdk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int i;
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struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
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const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
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for (i = 0; pll_cfg[i].rate != 0; i++) {
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if (pll_cfg[i].rate == rate) {
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return clk->pll_devdata->update_rate(clk, rate,
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&pll_cfg[i]);
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}
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}
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dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
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parent_rate);
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return -EINVAL;
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}
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static const struct clk_ops hsdk_pll_ops = {
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.recalc_rate = hsdk_pll_recalc_rate,
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.round_rate = hsdk_pll_round_rate,
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.set_rate = hsdk_pll_set_rate,
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};
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static int hsdk_pll_clk_probe(struct platform_device *pdev)
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{
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int ret;
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struct resource *mem;
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const char *parent_name;
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unsigned int num_parents;
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struct hsdk_pll_clk *pll_clk;
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struct clk_init_data init = { };
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struct device *dev = &pdev->dev;
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pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pll_clk->regs = devm_ioremap_resource(dev, mem);
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if (IS_ERR(pll_clk->regs))
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return PTR_ERR(pll_clk->regs);
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init.name = dev->of_node->name;
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init.ops = &hsdk_pll_ops;
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parent_name = of_clk_get_parent_name(dev->of_node, 0);
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init.parent_names = &parent_name;
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num_parents = of_clk_get_parent_count(dev->of_node);
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if (num_parents == 0 || num_parents > CGU_PLL_SOURCE_MAX) {
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dev_err(dev, "wrong clock parents number: %u\n", num_parents);
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return -EINVAL;
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}
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init.num_parents = num_parents;
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pll_clk->hw.init = &init;
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pll_clk->dev = dev;
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pll_clk->pll_devdata = of_device_get_match_data(dev);
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if (!pll_clk->pll_devdata) {
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dev_err(dev, "No OF match data provided\n");
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return -EINVAL;
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}
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ret = devm_clk_hw_register(dev, &pll_clk->hw);
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if (ret) {
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dev_err(dev, "failed to register %s clock\n", init.name);
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return ret;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
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&pll_clk->hw);
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}
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static int hsdk_pll_clk_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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return 0;
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}
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static void __init of_hsdk_pll_clk_setup(struct device_node *node)
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{
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int ret;
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const char *parent_name;
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unsigned int num_parents;
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struct hsdk_pll_clk *pll_clk;
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struct clk_init_data init = { };
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return;
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pll_clk->regs = of_iomap(node, 0);
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if (!pll_clk->regs) {
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pr_err("failed to map pll registers\n");
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goto err_free_pll_clk;
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}
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pll_clk->spec_regs = of_iomap(node, 1);
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if (!pll_clk->spec_regs) {
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pr_err("failed to map pll registers\n");
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goto err_unmap_comm_regs;
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}
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init.name = node->name;
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init.ops = &hsdk_pll_ops;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents > CGU_PLL_SOURCE_MAX) {
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pr_err("too much clock parents: %u\n", num_parents);
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goto err_unmap_spec_regs;
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}
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init.num_parents = num_parents;
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pll_clk->hw.init = &init;
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pll_clk->pll_devdata = &core_pll_devdata;
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ret = clk_hw_register(NULL, &pll_clk->hw);
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if (ret) {
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pr_err("failed to register %pOFn clock\n", node);
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goto err_unmap_spec_regs;
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}
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ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
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if (ret) {
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pr_err("failed to add hw provider for %pOFn clock\n", node);
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goto err_unmap_spec_regs;
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}
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return;
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err_unmap_spec_regs:
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iounmap(pll_clk->spec_regs);
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err_unmap_comm_regs:
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iounmap(pll_clk->regs);
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err_free_pll_clk:
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kfree(pll_clk);
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}
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/* Core PLL needed early for ARC cpus timers */
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CLK_OF_DECLARE(hsdk_pll_clock, "snps,hsdk-core-pll-clock",
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of_hsdk_pll_clk_setup);
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static const struct of_device_id hsdk_pll_clk_id[] = {
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{ .compatible = "snps,hsdk-gp-pll-clock", .data = &sdt_pll_devdata},
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{ .compatible = "snps,hsdk-hdmi-pll-clock", .data = &hdmi_pll_devdata},
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{ }
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};
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static struct platform_driver hsdk_pll_clk_driver = {
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.driver = {
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.name = "hsdk-gp-pll-clock",
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.of_match_table = hsdk_pll_clk_id,
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},
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.probe = hsdk_pll_clk_probe,
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.remove = hsdk_pll_clk_remove,
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};
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builtin_platform_driver(hsdk_pll_clk_driver);
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