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1fdff40702
* Fix the RISC-V section of the generic CPU idle bindings to comply with the recently tightened DT schema. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAmJHkg0THHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQfnuD/0R2okYlU+nTxmuNQmYCriX7CQUrBzq wL/LFg7TBI3ypNLb0vL9fa+3WCS8iLP1xGTYOKALaJBwzvnOuxhbkvYMp8+tWnfj m7CUU0M6sMXjqyS8qXysIS+RcowLGJpu8aPWSa4YbtV30z2yLzxhnpBOiTbhOzqV coCvYLYSTVOPZ68nizU8V7HhARL3MzZl9WMFSXPW/jiXA0WQYI92xp9ZF21CkiM/ tTePiy93BxAzshGVLoHBp83UKMabxeD9kKiwkt497p08U3NLfbq6AjB91MwuWtzo ZeM3oYEVJkkbVAJzZQWYxXigjzfeY0LEi92DBWMRtTnEMXacpglZUNWEbRFntI3v yIw873qtzsmsYLvMzapP2oDA0ZO2ZI8vLVqml5ABhgPs8ADBviCFyB68jcvevKad iXNfhOozjMXN/9D7psbzuiPqPDSo3ihae8E4Op3Z3NEJqyQxyDXuhgNyn1voYXYP A6PyF4KP2es4Q/NWs8tut5U8shaZ8OxR1WbjdguhXZG9V+CEPWVTMQpOhXKpH8TA dr4Cg5MnUaPnjulqmzmWJgj5Sp603AfexznKoa73A40BDrXY/wXSdpijCbai384Q NC1aGuoo05D09mYdOrkfzE7Ub/edH1ry0nY9mCU/IoRsp/lS+FoUS3Ljy4YamDpJ r/d4ftpuvFmC6A== =hBrc -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fix from Palmer Dabbelt: - Fix the RISC-V section of the generic CPU idle bindings to comply with the recently tightened DT schema. * tag 'riscv-for-linus-5.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: dt-bindings: Fix phandle-array issues in the idle-states bindings |
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