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1a0f7ed3ab
Add support for cdn DP controller which is embedded in the rk3399 SoCs. The DP is compliant with DisplayPort Specification, Version 1.3, This IP is compatible with the rockchip type-c PHY IP. There is a uCPU in DP controller, it need a firmware to work, please put the firmware file to /lib/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong <zyw@rock-chips.com> [seanpaul fixed up some races between the worker and modeset] [seanpaul squashed ~15 commits from chromium.org gerrit] Signed-off-by: Sean Paul <seanpaul@chromium.org> [groeck fixed compilation errors when building as module] Signed-off-by: Guenter Roeck <groeck@chromium.org>
421 lines
14 KiB
C
421 lines
14 KiB
C
/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drm/drmP.h>
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#include <linux/kernel.h>
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#include <linux/component.h>
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#include "rockchip_drm_vop.h"
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#include "rockchip_vop_reg.h"
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#define VOP_REG(off, _mask, s) \
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{.offset = off, \
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.mask = _mask, \
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.shift = s, \
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.write_mask = false,}
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#define VOP_REG_MASK(off, _mask, s) \
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{.offset = off, \
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.mask = _mask, \
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.shift = s, \
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.write_mask = true,}
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static const uint32_t formats_win_full[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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DRM_FORMAT_NV12,
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DRM_FORMAT_NV16,
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DRM_FORMAT_NV24,
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};
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static const uint32_t formats_win_lite[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR565,
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};
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static const struct vop_scl_regs rk3036_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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};
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static const struct vop_win_phy rk3036_win0_data = {
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.scl = &rk3036_win_scl,
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.data_formats = formats_win_full,
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.nformats = ARRAY_SIZE(formats_win_full),
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.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
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.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
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.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
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.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
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.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
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};
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static const struct vop_win_phy rk3036_win1_data = {
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.data_formats = formats_win_lite,
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.nformats = ARRAY_SIZE(formats_win_lite),
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.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
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.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
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.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
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.act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
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};
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static const struct vop_win_data rk3036_vop_win_data[] = {
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{ .base = 0x00, .phy = &rk3036_win0_data,
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.type = DRM_PLANE_TYPE_PRIMARY },
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{ .base = 0x00, .phy = &rk3036_win1_data,
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.type = DRM_PLANE_TYPE_CURSOR },
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};
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static const int rk3036_vop_intrs[] = {
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DSP_HOLD_VALID_INTR,
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FS_INTR,
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LINE_FLAG_INTR,
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BUS_ERROR_INTR,
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};
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static const struct vop_intr rk3036_intr = {
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.intrs = rk3036_vop_intrs,
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.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
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.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
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.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
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.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
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};
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static const struct vop_ctrl rk3036_ctrl_data = {
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.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
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.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
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.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
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.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
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.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
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.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
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};
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static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
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{RK3036_DSP_CTRL1, 0x00000000},
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};
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static const struct vop_data rk3036_vop = {
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.init_table = rk3036_vop_init_reg_table,
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.table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
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.ctrl = &rk3036_ctrl_data,
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.intr = &rk3036_intr,
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.win = rk3036_vop_win_data,
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.win_size = ARRAY_SIZE(rk3036_vop_win_data),
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};
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static const struct vop_scl_extension rk3288_win_full_scl_ext = {
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.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
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.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
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.cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
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.cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
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.cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
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.yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
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.yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
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.yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
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.yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
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.yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
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.line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
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.cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
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.yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
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.vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
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.vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
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.vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
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.vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
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.bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
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.cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
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.yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
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.lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
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};
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static const struct vop_scl_regs rk3288_win_full_scl = {
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.ext = &rk3288_win_full_scl_ext,
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.scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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.scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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.scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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};
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static const struct vop_win_phy rk3288_win01_data = {
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.scl = &rk3288_win_full_scl,
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.data_formats = formats_win_full,
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.nformats = ARRAY_SIZE(formats_win_full),
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.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
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.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
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.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
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.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
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.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
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.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
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};
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static const struct vop_win_phy rk3288_win23_data = {
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.data_formats = formats_win_lite,
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.nformats = ARRAY_SIZE(formats_win_lite),
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.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
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.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
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.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
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.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
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.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
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};
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static const struct vop_ctrl rk3288_ctrl_data = {
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.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
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.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
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.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
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.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
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.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
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.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
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.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
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.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
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.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
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.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
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.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
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.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
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.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
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.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
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.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
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};
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static const struct vop_reg_data rk3288_init_reg_table[] = {
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{RK3288_SYS_CTRL, 0x00c00000},
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{RK3288_DSP_CTRL0, 0x00000000},
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{RK3288_WIN0_CTRL0, 0x00000080},
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{RK3288_WIN1_CTRL0, 0x00000080},
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/* TODO: Win2/3 support multiple area function, but we haven't found
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* a suitable way to use it yet, so let's just use them as other windows
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* with only area 0 enabled.
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*/
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{RK3288_WIN2_CTRL0, 0x00000010},
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{RK3288_WIN3_CTRL0, 0x00000010},
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};
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/*
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* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
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* special support to get alpha blending working. For now, just use overlay
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* window 3 for the drm cursor.
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*
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*/
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static const struct vop_win_data rk3288_vop_win_data[] = {
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{ .base = 0x00, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_PRIMARY },
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{ .base = 0x40, .phy = &rk3288_win01_data,
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.type = DRM_PLANE_TYPE_OVERLAY },
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{ .base = 0x00, .phy = &rk3288_win23_data,
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.type = DRM_PLANE_TYPE_OVERLAY },
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{ .base = 0x50, .phy = &rk3288_win23_data,
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.type = DRM_PLANE_TYPE_CURSOR },
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};
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static const int rk3288_vop_intrs[] = {
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DSP_HOLD_VALID_INTR,
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FS_INTR,
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LINE_FLAG_INTR,
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BUS_ERROR_INTR,
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};
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static const struct vop_intr rk3288_vop_intr = {
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.intrs = rk3288_vop_intrs,
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.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
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.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
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.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
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.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
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};
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static const struct vop_data rk3288_vop = {
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.init_table = rk3288_init_reg_table,
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.table_size = ARRAY_SIZE(rk3288_init_reg_table),
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.intr = &rk3288_vop_intr,
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.ctrl = &rk3288_ctrl_data,
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.win = rk3288_vop_win_data,
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.win_size = ARRAY_SIZE(rk3288_vop_win_data),
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};
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static const struct vop_ctrl rk3399_ctrl_data = {
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.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
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.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
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.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
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.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
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.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
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.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
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.mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
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.dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
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.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
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.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
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.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
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.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
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.dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
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.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
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.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
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.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
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.htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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.hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
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.vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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.line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
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.line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
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.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
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|
};
|
|
|
|
static const int rk3399_vop_intrs[] = {
|
|
FS_INTR,
|
|
0, 0,
|
|
LINE_FLAG_INTR,
|
|
0,
|
|
BUS_ERROR_INTR,
|
|
0, 0, 0, 0, 0, 0, 0,
|
|
DSP_HOLD_VALID_INTR,
|
|
};
|
|
|
|
static const struct vop_intr rk3399_vop_intr = {
|
|
.intrs = rk3399_vop_intrs,
|
|
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
|
|
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
|
|
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
|
|
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
|
|
};
|
|
|
|
static const struct vop_reg_data rk3399_init_reg_table[] = {
|
|
{RK3399_SYS_CTRL, 0x2000f800},
|
|
{RK3399_DSP_CTRL0, 0x00000000},
|
|
{RK3399_WIN0_CTRL0, 0x00000080},
|
|
{RK3399_WIN1_CTRL0, 0x00000080},
|
|
/* TODO: Win2/3 support multiple area function, but we haven't found
|
|
* a suitable way to use it yet, so let's just use them as other windows
|
|
* with only area 0 enabled.
|
|
*/
|
|
{RK3399_WIN2_CTRL0, 0x00000010},
|
|
{RK3399_WIN3_CTRL0, 0x00000010},
|
|
};
|
|
|
|
static const struct vop_data rk3399_vop_big = {
|
|
.init_table = rk3399_init_reg_table,
|
|
.table_size = ARRAY_SIZE(rk3399_init_reg_table),
|
|
.intr = &rk3399_vop_intr,
|
|
.ctrl = &rk3399_ctrl_data,
|
|
/*
|
|
* rk3399 vop big windows register layout is same as rk3288.
|
|
*/
|
|
.win = rk3288_vop_win_data,
|
|
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
|
|
};
|
|
|
|
static const struct vop_win_data rk3399_vop_lit_win_data[] = {
|
|
{ .base = 0x00, .phy = &rk3288_win01_data,
|
|
.type = DRM_PLANE_TYPE_PRIMARY },
|
|
{ .base = 0x00, .phy = &rk3288_win23_data,
|
|
.type = DRM_PLANE_TYPE_CURSOR},
|
|
};
|
|
|
|
static const struct vop_data rk3399_vop_lit = {
|
|
.init_table = rk3399_init_reg_table,
|
|
.table_size = ARRAY_SIZE(rk3399_init_reg_table),
|
|
.intr = &rk3399_vop_intr,
|
|
.ctrl = &rk3399_ctrl_data,
|
|
/*
|
|
* rk3399 vop lit windows register layout is same as rk3288,
|
|
* but cut off the win1 and win3 windows.
|
|
*/
|
|
.win = rk3399_vop_lit_win_data,
|
|
.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
|
|
};
|
|
|
|
static const struct of_device_id vop_driver_dt_match[] = {
|
|
{ .compatible = "rockchip,rk3036-vop",
|
|
.data = &rk3036_vop },
|
|
{ .compatible = "rockchip,rk3288-vop",
|
|
.data = &rk3288_vop },
|
|
{ .compatible = "rockchip,rk3399-vop-big",
|
|
.data = &rk3399_vop_big },
|
|
{ .compatible = "rockchip,rk3399-vop-lit",
|
|
.data = &rk3399_vop_lit },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
|
|
|
|
static int vop_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
|
|
if (!dev->of_node) {
|
|
dev_err(dev, "can't find vop devices\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return component_add(dev, &vop_component_ops);
|
|
}
|
|
|
|
static int vop_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &vop_component_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver vop_platform_driver = {
|
|
.probe = vop_probe,
|
|
.remove = vop_remove,
|
|
.driver = {
|
|
.name = "rockchip-vop",
|
|
.of_match_table = of_match_ptr(vop_driver_dt_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(vop_platform_driver);
|
|
|
|
MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
|
|
MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
|
|
MODULE_LICENSE("GPL v2");
|