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94330fbe08
Avoid cluttering up the kallsyms symbol table with entries that should not end up in things like backtraces, as they have undescriptive and generated identifiers. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
701 lines
14 KiB
ArmAsm
701 lines
14 KiB
ArmAsm
/*
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* Implement fast SHA-1 with AVX2 instructions. (x86_64)
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* Contact Information:
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* Ilya Albrekht <ilya.albrekht@intel.com>
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* Maxim Locktyukhin <maxim.locktyukhin@intel.com>
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* Ronen Zohar <ronen.zohar@intel.com>
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* Chandramouli Narayanan <mouli@linux.intel.com>
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*
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* BSD LICENSE
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*
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* Copyright(c) 2014 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* SHA-1 implementation with Intel(R) AVX2 instruction set extensions.
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*
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*This implementation is based on the previous SSSE3 release:
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*Visit http://software.intel.com/en-us/articles/
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*and refer to improving-the-performance-of-the-secure-hash-algorithm-1/
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*
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*Updates 20-byte SHA-1 record at start of 'state', from 'input', for
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*even number of 'blocks' consecutive 64-byte blocks.
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*
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*extern "C" void sha1_transform_avx2(
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* struct sha1_state *state, const u8* input, int blocks );
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*/
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#include <linux/linkage.h>
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#define CTX %rdi /* arg1 */
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#define BUF %rsi /* arg2 */
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#define CNT %rdx /* arg3 */
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#define REG_A %ecx
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#define REG_B %esi
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#define REG_C %edi
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#define REG_D %eax
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#define REG_E %edx
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#define REG_TB %ebx
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#define REG_TA %r12d
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#define REG_RA %rcx
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#define REG_RB %rsi
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#define REG_RC %rdi
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#define REG_RD %rax
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#define REG_RE %rdx
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#define REG_RTA %r12
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#define REG_RTB %rbx
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#define REG_T1 %r11d
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#define xmm_mov vmovups
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#define avx2_zeroupper vzeroupper
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#define RND_F1 1
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#define RND_F2 2
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#define RND_F3 3
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.macro REGALLOC
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.set A, REG_A
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.set B, REG_B
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.set C, REG_C
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.set D, REG_D
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.set E, REG_E
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.set TB, REG_TB
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.set TA, REG_TA
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.set RA, REG_RA
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.set RB, REG_RB
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.set RC, REG_RC
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.set RD, REG_RD
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.set RE, REG_RE
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.set RTA, REG_RTA
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.set RTB, REG_RTB
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.set T1, REG_T1
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.endm
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#define HASH_PTR %r9
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#define BLOCKS_CTR %r8
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#define BUFFER_PTR %r10
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#define BUFFER_PTR2 %r13
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#define PRECALC_BUF %r14
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#define WK_BUF %r15
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#define W_TMP %xmm0
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#define WY_TMP %ymm0
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#define WY_TMP2 %ymm9
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# AVX2 variables
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#define WY0 %ymm3
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#define WY4 %ymm5
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#define WY08 %ymm7
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#define WY12 %ymm8
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#define WY16 %ymm12
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#define WY20 %ymm13
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#define WY24 %ymm14
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#define WY28 %ymm15
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#define YMM_SHUFB_BSWAP %ymm10
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/*
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* Keep 2 iterations precalculated at a time:
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* - 80 DWORDs per iteration * 2
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*/
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#define W_SIZE (80*2*2 +16)
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#define WK(t) ((((t) % 80) / 4)*32 + ( (t) % 4)*4 + ((t)/80)*16 )(WK_BUF)
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#define PRECALC_WK(t) ((t)*2*2)(PRECALC_BUF)
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.macro UPDATE_HASH hash, val
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add \hash, \val
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mov \val, \hash
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.endm
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.macro PRECALC_RESET_WY
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.set WY_00, WY0
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.set WY_04, WY4
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.set WY_08, WY08
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.set WY_12, WY12
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.set WY_16, WY16
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.set WY_20, WY20
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.set WY_24, WY24
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.set WY_28, WY28
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.set WY_32, WY_00
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.endm
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.macro PRECALC_ROTATE_WY
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/* Rotate macros */
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.set WY_32, WY_28
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.set WY_28, WY_24
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.set WY_24, WY_20
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.set WY_20, WY_16
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.set WY_16, WY_12
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.set WY_12, WY_08
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.set WY_08, WY_04
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.set WY_04, WY_00
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.set WY_00, WY_32
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/* Define register aliases */
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.set WY, WY_00
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.set WY_minus_04, WY_04
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.set WY_minus_08, WY_08
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.set WY_minus_12, WY_12
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.set WY_minus_16, WY_16
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.set WY_minus_20, WY_20
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.set WY_minus_24, WY_24
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.set WY_minus_28, WY_28
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.set WY_minus_32, WY
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.endm
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.macro PRECALC_00_15
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.if (i == 0) # Initialize and rotate registers
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PRECALC_RESET_WY
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PRECALC_ROTATE_WY
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.endif
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/* message scheduling pre-compute for rounds 0-15 */
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.if ((i & 7) == 0)
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/*
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* blended AVX2 and ALU instruction scheduling
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* 1 vector iteration per 8 rounds
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*/
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vmovdqu (i * 2)(BUFFER_PTR), W_TMP
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.elseif ((i & 7) == 1)
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vinsertf128 $1, ((i-1) * 2)(BUFFER_PTR2),\
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WY_TMP, WY_TMP
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.elseif ((i & 7) == 2)
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vpshufb YMM_SHUFB_BSWAP, WY_TMP, WY
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.elseif ((i & 7) == 4)
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vpaddd K_XMM + K_XMM_AR(%rip), WY, WY_TMP
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.elseif ((i & 7) == 7)
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vmovdqu WY_TMP, PRECALC_WK(i&~7)
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PRECALC_ROTATE_WY
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.endif
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.endm
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.macro PRECALC_16_31
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/*
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* message scheduling pre-compute for rounds 16-31
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* calculating last 32 w[i] values in 8 XMM registers
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* pre-calculate K+w[i] values and store to mem
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* for later load by ALU add instruction
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*
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* "brute force" vectorization for rounds 16-31 only
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* due to w[i]->w[i-3] dependency
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*/
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.if ((i & 7) == 0)
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/*
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* blended AVX2 and ALU instruction scheduling
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* 1 vector iteration per 8 rounds
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*/
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/* w[i-14] */
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vpalignr $8, WY_minus_16, WY_minus_12, WY
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vpsrldq $4, WY_minus_04, WY_TMP /* w[i-3] */
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.elseif ((i & 7) == 1)
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vpxor WY_minus_08, WY, WY
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vpxor WY_minus_16, WY_TMP, WY_TMP
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.elseif ((i & 7) == 2)
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vpxor WY_TMP, WY, WY
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vpslldq $12, WY, WY_TMP2
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.elseif ((i & 7) == 3)
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vpslld $1, WY, WY_TMP
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vpsrld $31, WY, WY
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.elseif ((i & 7) == 4)
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vpor WY, WY_TMP, WY_TMP
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vpslld $2, WY_TMP2, WY
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.elseif ((i & 7) == 5)
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vpsrld $30, WY_TMP2, WY_TMP2
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vpxor WY, WY_TMP, WY_TMP
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.elseif ((i & 7) == 7)
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vpxor WY_TMP2, WY_TMP, WY
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vpaddd K_XMM + K_XMM_AR(%rip), WY, WY_TMP
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vmovdqu WY_TMP, PRECALC_WK(i&~7)
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PRECALC_ROTATE_WY
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.endif
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.endm
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.macro PRECALC_32_79
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/*
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* in SHA-1 specification:
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* w[i] = (w[i-3] ^ w[i-8] ^ w[i-14] ^ w[i-16]) rol 1
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* instead we do equal:
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* w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2
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* allows more efficient vectorization
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* since w[i]=>w[i-3] dependency is broken
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*/
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.if ((i & 7) == 0)
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/*
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* blended AVX2 and ALU instruction scheduling
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* 1 vector iteration per 8 rounds
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*/
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vpalignr $8, WY_minus_08, WY_minus_04, WY_TMP
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.elseif ((i & 7) == 1)
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/* W is W_minus_32 before xor */
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vpxor WY_minus_28, WY, WY
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.elseif ((i & 7) == 2)
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vpxor WY_minus_16, WY_TMP, WY_TMP
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.elseif ((i & 7) == 3)
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vpxor WY_TMP, WY, WY
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.elseif ((i & 7) == 4)
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vpslld $2, WY, WY_TMP
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.elseif ((i & 7) == 5)
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vpsrld $30, WY, WY
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vpor WY, WY_TMP, WY
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.elseif ((i & 7) == 7)
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vpaddd K_XMM + K_XMM_AR(%rip), WY, WY_TMP
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vmovdqu WY_TMP, PRECALC_WK(i&~7)
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PRECALC_ROTATE_WY
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.endif
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.endm
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.macro PRECALC r, s
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.set i, \r
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.if (i < 40)
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.set K_XMM, 32*0
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.elseif (i < 80)
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.set K_XMM, 32*1
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.elseif (i < 120)
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.set K_XMM, 32*2
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.else
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.set K_XMM, 32*3
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.endif
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.if (i<32)
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PRECALC_00_15 \s
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.elseif (i<64)
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PRECALC_16_31 \s
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.elseif (i < 160)
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PRECALC_32_79 \s
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.endif
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.endm
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.macro ROTATE_STATE
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.set T_REG, E
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.set E, D
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.set D, C
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.set C, B
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.set B, TB
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.set TB, A
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.set A, T_REG
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.set T_REG, RE
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.set RE, RD
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.set RD, RC
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.set RC, RB
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.set RB, RTB
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.set RTB, RA
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.set RA, T_REG
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.endm
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/* Macro relies on saved ROUND_Fx */
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.macro RND_FUN f, r
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.if (\f == RND_F1)
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ROUND_F1 \r
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.elseif (\f == RND_F2)
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ROUND_F2 \r
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.elseif (\f == RND_F3)
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ROUND_F3 \r
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.endif
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.endm
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.macro RR r
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.set round_id, (\r % 80)
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.if (round_id == 0) /* Precalculate F for first round */
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.set ROUND_FUNC, RND_F1
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mov B, TB
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rorx $(32-30), B, B /* b>>>2 */
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andn D, TB, T1
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and C, TB
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xor T1, TB
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.endif
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RND_FUN ROUND_FUNC, \r
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ROTATE_STATE
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.if (round_id == 18)
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.set ROUND_FUNC, RND_F2
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.elseif (round_id == 38)
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.set ROUND_FUNC, RND_F3
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.elseif (round_id == 58)
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.set ROUND_FUNC, RND_F2
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.endif
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.set round_id, ( (\r+1) % 80)
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RND_FUN ROUND_FUNC, (\r+1)
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ROTATE_STATE
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.endm
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.macro ROUND_F1 r
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add WK(\r), E
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andn C, A, T1 /* ~b&d */
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lea (RE,RTB), E /* Add F from the previous round */
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rorx $(32-5), A, TA /* T2 = A >>> 5 */
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rorx $(32-30),A, TB /* b>>>2 for next round */
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PRECALC (\r) /* msg scheduling for next 2 blocks */
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/*
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* Calculate F for the next round
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* (b & c) ^ andn[b, d]
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*/
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and B, A /* b&c */
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xor T1, A /* F1 = (b&c) ^ (~b&d) */
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lea (RE,RTA), E /* E += A >>> 5 */
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.endm
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.macro ROUND_F2 r
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add WK(\r), E
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lea (RE,RTB), E /* Add F from the previous round */
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/* Calculate F for the next round */
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rorx $(32-5), A, TA /* T2 = A >>> 5 */
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.if ((round_id) < 79)
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rorx $(32-30), A, TB /* b>>>2 for next round */
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.endif
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PRECALC (\r) /* msg scheduling for next 2 blocks */
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.if ((round_id) < 79)
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xor B, A
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.endif
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add TA, E /* E += A >>> 5 */
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.if ((round_id) < 79)
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xor C, A
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.endif
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.endm
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.macro ROUND_F3 r
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add WK(\r), E
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PRECALC (\r) /* msg scheduling for next 2 blocks */
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lea (RE,RTB), E /* Add F from the previous round */
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mov B, T1
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or A, T1
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rorx $(32-5), A, TA /* T2 = A >>> 5 */
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rorx $(32-30), A, TB /* b>>>2 for next round */
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/* Calculate F for the next round
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* (b and c) or (d and (b or c))
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*/
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and C, T1
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and B, A
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or T1, A
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add TA, E /* E += A >>> 5 */
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.endm
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/* Add constant only if (%2 > %3) condition met (uses RTA as temp)
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* %1 + %2 >= %3 ? %4 : 0
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*/
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.macro ADD_IF_GE a, b, c, d
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mov \a, RTA
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add $\d, RTA
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cmp $\c, \b
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cmovge RTA, \a
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.endm
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/*
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* macro implements 80 rounds of SHA-1, for multiple blocks with s/w pipelining
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*/
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.macro SHA1_PIPELINED_MAIN_BODY
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REGALLOC
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mov (HASH_PTR), A
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mov 4(HASH_PTR), B
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mov 8(HASH_PTR), C
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mov 12(HASH_PTR), D
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mov 16(HASH_PTR), E
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mov %rsp, PRECALC_BUF
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lea (2*4*80+32)(%rsp), WK_BUF
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# Precalc WK for first 2 blocks
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ADD_IF_GE BUFFER_PTR2, BLOCKS_CTR, 2, 64
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.set i, 0
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.rept 160
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PRECALC i
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.set i, i + 1
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.endr
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/* Go to next block if needed */
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ADD_IF_GE BUFFER_PTR, BLOCKS_CTR, 3, 128
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ADD_IF_GE BUFFER_PTR2, BLOCKS_CTR, 4, 128
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xchg WK_BUF, PRECALC_BUF
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.align 32
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.L_loop:
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/*
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* code loops through more than one block
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* we use K_BASE value as a signal of a last block,
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* it is set below by: cmovae BUFFER_PTR, K_BASE
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*/
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test BLOCKS_CTR, BLOCKS_CTR
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jnz .L_begin
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.align 32
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jmp .L_end
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.align 32
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.L_begin:
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/*
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|
* Do first block
|
|
* rounds: 0,2,4,6,8
|
|
*/
|
|
.set j, 0
|
|
.rept 5
|
|
RR j
|
|
.set j, j+2
|
|
.endr
|
|
|
|
/*
|
|
* rounds:
|
|
* 10,12,14,16,18
|
|
* 20,22,24,26,28
|
|
* 30,32,34,36,38
|
|
* 40,42,44,46,48
|
|
* 50,52,54,56,58
|
|
*/
|
|
.rept 25
|
|
RR j
|
|
.set j, j+2
|
|
.endr
|
|
|
|
/* Update Counter */
|
|
sub $1, BLOCKS_CTR
|
|
/* Move to the next block only if needed*/
|
|
ADD_IF_GE BUFFER_PTR, BLOCKS_CTR, 4, 128
|
|
/*
|
|
* rounds
|
|
* 60,62,64,66,68
|
|
* 70,72,74,76,78
|
|
*/
|
|
.rept 10
|
|
RR j
|
|
.set j, j+2
|
|
.endr
|
|
|
|
UPDATE_HASH (HASH_PTR), A
|
|
UPDATE_HASH 4(HASH_PTR), TB
|
|
UPDATE_HASH 8(HASH_PTR), C
|
|
UPDATE_HASH 12(HASH_PTR), D
|
|
UPDATE_HASH 16(HASH_PTR), E
|
|
|
|
test BLOCKS_CTR, BLOCKS_CTR
|
|
jz .L_loop
|
|
|
|
mov TB, B
|
|
|
|
/* Process second block */
|
|
/*
|
|
* rounds
|
|
* 0+80, 2+80, 4+80, 6+80, 8+80
|
|
* 10+80,12+80,14+80,16+80,18+80
|
|
*/
|
|
|
|
.set j, 0
|
|
.rept 10
|
|
RR j+80
|
|
.set j, j+2
|
|
.endr
|
|
|
|
/*
|
|
* rounds
|
|
* 20+80,22+80,24+80,26+80,28+80
|
|
* 30+80,32+80,34+80,36+80,38+80
|
|
*/
|
|
.rept 10
|
|
RR j+80
|
|
.set j, j+2
|
|
.endr
|
|
|
|
/*
|
|
* rounds
|
|
* 40+80,42+80,44+80,46+80,48+80
|
|
* 50+80,52+80,54+80,56+80,58+80
|
|
*/
|
|
.rept 10
|
|
RR j+80
|
|
.set j, j+2
|
|
.endr
|
|
|
|
/* update counter */
|
|
sub $1, BLOCKS_CTR
|
|
/* Move to the next block only if needed*/
|
|
ADD_IF_GE BUFFER_PTR2, BLOCKS_CTR, 4, 128
|
|
|
|
/*
|
|
* rounds
|
|
* 60+80,62+80,64+80,66+80,68+80
|
|
* 70+80,72+80,74+80,76+80,78+80
|
|
*/
|
|
.rept 10
|
|
RR j+80
|
|
.set j, j+2
|
|
.endr
|
|
|
|
UPDATE_HASH (HASH_PTR), A
|
|
UPDATE_HASH 4(HASH_PTR), TB
|
|
UPDATE_HASH 8(HASH_PTR), C
|
|
UPDATE_HASH 12(HASH_PTR), D
|
|
UPDATE_HASH 16(HASH_PTR), E
|
|
|
|
/* Reset state for AVX2 reg permutation */
|
|
mov A, TA
|
|
mov TB, A
|
|
mov C, TB
|
|
mov E, C
|
|
mov D, B
|
|
mov TA, D
|
|
|
|
REGALLOC
|
|
|
|
xchg WK_BUF, PRECALC_BUF
|
|
|
|
jmp .L_loop
|
|
|
|
.align 32
|
|
.L_end:
|
|
|
|
.endm
|
|
/*
|
|
* macro implements SHA-1 function's body for several 64-byte blocks
|
|
* param: function's name
|
|
*/
|
|
.macro SHA1_VECTOR_ASM name
|
|
SYM_FUNC_START(\name)
|
|
|
|
push %rbx
|
|
push %r12
|
|
push %r13
|
|
push %r14
|
|
push %r15
|
|
|
|
RESERVE_STACK = (W_SIZE*4 + 8+24)
|
|
|
|
/* Align stack */
|
|
push %rbp
|
|
mov %rsp, %rbp
|
|
and $~(0x20-1), %rsp
|
|
sub $RESERVE_STACK, %rsp
|
|
|
|
avx2_zeroupper
|
|
|
|
/* Setup initial values */
|
|
mov CTX, HASH_PTR
|
|
mov BUF, BUFFER_PTR
|
|
|
|
mov BUF, BUFFER_PTR2
|
|
mov CNT, BLOCKS_CTR
|
|
|
|
xmm_mov BSWAP_SHUFB_CTL(%rip), YMM_SHUFB_BSWAP
|
|
|
|
SHA1_PIPELINED_MAIN_BODY
|
|
|
|
avx2_zeroupper
|
|
|
|
mov %rbp, %rsp
|
|
pop %rbp
|
|
|
|
pop %r15
|
|
pop %r14
|
|
pop %r13
|
|
pop %r12
|
|
pop %rbx
|
|
|
|
RET
|
|
|
|
SYM_FUNC_END(\name)
|
|
.endm
|
|
|
|
.section .rodata
|
|
|
|
#define K1 0x5a827999
|
|
#define K2 0x6ed9eba1
|
|
#define K3 0x8f1bbcdc
|
|
#define K4 0xca62c1d6
|
|
|
|
.align 128
|
|
K_XMM_AR:
|
|
.long K1, K1, K1, K1
|
|
.long K1, K1, K1, K1
|
|
.long K2, K2, K2, K2
|
|
.long K2, K2, K2, K2
|
|
.long K3, K3, K3, K3
|
|
.long K3, K3, K3, K3
|
|
.long K4, K4, K4, K4
|
|
.long K4, K4, K4, K4
|
|
|
|
BSWAP_SHUFB_CTL:
|
|
.long 0x00010203
|
|
.long 0x04050607
|
|
.long 0x08090a0b
|
|
.long 0x0c0d0e0f
|
|
.long 0x00010203
|
|
.long 0x04050607
|
|
.long 0x08090a0b
|
|
.long 0x0c0d0e0f
|
|
.text
|
|
|
|
SHA1_VECTOR_ASM sha1_transform_avx2
|