Suravee Suthikulpanit 1e98a35da4 iommu/amd: Introduce Support for Extended Feature 2 Register ... AMD IOMMU spec introduces additional extended feature register in the IVRS IVHD offset 80h (for IVHD type 11h and 40h) and MMIO offset 1A0h. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Link: https://lore.kernel.org/r/20220713225651.20758-3-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>		2022-07-15 10:41:02 +02:00
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amd_iommu_types.h	iommu/amd: Introduce Support for Extended Feature 2 Register	2022-07-15 10:41:02 +02:00
amd_iommu.h	iommu/amd: Include PCI segment ID when initialize IOMMU	2022-07-07 09:37:51 +02:00
debugfs.c
init.c	iommu/amd: Introduce Support for Extended Feature 2 Register	2022-07-15 10:41:02 +02:00
io_pgtable.c	iommu/amd: Use try_cmpxchg64 in alloc_pte and free_clear_pte	2022-06-23 09:43:31 +02:00
iommu_v2.c	iommu/amd: Update amd_iommu_fault structure to include PCI seg ID	2022-07-07 09:37:54 +02:00
iommu.c	iommu/amd: Update amd_iommu_fault structure to include PCI seg ID	2022-07-07 09:37:54 +02:00
Kconfig	iommu/amd: Prepare for generic IO page table framework	2021-01-28 16:51:17 +01:00
Makefile	iommu/amd: Prepare for generic IO page table framework	2021-01-28 16:51:17 +01:00
quirks.c	iommu/amd: Include PCI segment ID when initialize IOMMU	2022-07-07 09:37:51 +02:00