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b0d0bf581f
Use drmm_simple_encoder_alloc() to align encoder memory lifetime with the drm device. drm_encoder_cleanup() is called automatically before the memory is freed. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
755 lines
20 KiB
C
755 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* i.MX drm driver - LVDS display bridge
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*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/regmap.h>
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#include <linux/videodev2.h>
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#include <video/of_display_timing.h>
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#include <video/of_videomode.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "imx-drm.h"
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#define DRIVER_NAME "imx-ldb"
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#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
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#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
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#define LDB_CH0_MODE_EN_MASK (3 << 0)
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#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
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#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
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#define LDB_CH1_MODE_EN_MASK (3 << 2)
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#define LDB_SPLIT_MODE_EN (1 << 4)
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#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
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#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
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#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
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#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
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#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
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#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
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#define LDB_BGREF_RMODE_INT (1 << 15)
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struct imx_ldb_channel;
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struct imx_ldb_encoder {
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struct drm_connector connector;
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struct drm_encoder encoder;
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struct imx_ldb_channel *channel;
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};
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struct imx_ldb;
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struct imx_ldb_channel {
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struct imx_ldb *ldb;
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/* Defines what is connected to the ldb, only one at a time */
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struct drm_panel *panel;
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struct drm_bridge *bridge;
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struct device_node *child;
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struct i2c_adapter *ddc;
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int chno;
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void *edid;
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struct drm_display_mode mode;
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int mode_valid;
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u32 bus_format;
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u32 bus_flags;
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};
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static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
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{
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return container_of(c, struct imx_ldb_encoder, connector)->channel;
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}
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static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
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{
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return container_of(e, struct imx_ldb_encoder, encoder)->channel;
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}
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struct bus_mux {
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int reg;
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int shift;
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int mask;
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};
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struct imx_ldb {
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struct regmap *regmap;
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struct device *dev;
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struct imx_ldb_channel channel[2];
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struct clk *clk[2]; /* our own clock */
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struct clk *clk_sel[4]; /* parent of display clock */
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struct clk *clk_parent[4]; /* original parent of clk_sel */
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struct clk *clk_pll[2]; /* upstream clock we can adjust */
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u32 ldb_ctrl;
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const struct bus_mux *lvds_mux;
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};
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static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
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u32 bus_format)
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{
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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switch (bus_format) {
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case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
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if (imx_ldb_ch->chno == 0 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
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if (imx_ldb_ch->chno == 1 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
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if (imx_ldb_ch->chno == 0 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
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LDB_BIT_MAP_CH0_JEIDA;
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if (imx_ldb_ch->chno == 1 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
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LDB_BIT_MAP_CH1_JEIDA;
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break;
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}
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}
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static int imx_ldb_connector_get_modes(struct drm_connector *connector)
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{
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struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
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int num_modes;
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num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
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if (num_modes > 0)
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return num_modes;
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if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
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imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
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if (imx_ldb_ch->edid) {
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drm_connector_update_edid_property(connector,
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imx_ldb_ch->edid);
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num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
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}
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if (imx_ldb_ch->mode_valid) {
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struct drm_display_mode *mode;
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mode = drm_mode_create(connector->dev);
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if (!mode)
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return -EINVAL;
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drm_mode_copy(mode, &imx_ldb_ch->mode);
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mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, mode);
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num_modes++;
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}
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return num_modes;
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}
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static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
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unsigned long serial_clk, unsigned long di_clk)
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{
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int ret;
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dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
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clk_get_rate(ldb->clk_pll[chno]), serial_clk);
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clk_set_rate(ldb->clk_pll[chno], serial_clk);
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dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
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clk_get_rate(ldb->clk_pll[chno]));
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dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
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clk_get_rate(ldb->clk[chno]),
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(long int)di_clk);
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clk_set_rate(ldb->clk[chno], di_clk);
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dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
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clk_get_rate(ldb->clk[chno]));
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/* set display clock mux to LDB input clock */
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ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
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if (ret)
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dev_err(ldb->dev,
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"unable to set di%d parent clock to ldb_di%d\n", mux,
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chno);
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}
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static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
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drm_panel_prepare(imx_ldb_ch->panel);
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if (dual) {
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clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
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clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
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clk_prepare_enable(ldb->clk[0]);
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clk_prepare_enable(ldb->clk[1]);
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} else {
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clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
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}
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if (imx_ldb_ch == &ldb->channel[0] || dual) {
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ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
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if (mux == 0 || ldb->lvds_mux)
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ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
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else if (mux == 1)
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ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
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}
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if (imx_ldb_ch == &ldb->channel[1] || dual) {
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ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
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if (mux == 1 || ldb->lvds_mux)
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ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
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else if (mux == 0)
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ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
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}
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if (ldb->lvds_mux) {
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const struct bus_mux *lvds_mux = NULL;
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if (imx_ldb_ch == &ldb->channel[0])
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lvds_mux = &ldb->lvds_mux[0];
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else if (imx_ldb_ch == &ldb->channel[1])
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lvds_mux = &ldb->lvds_mux[1];
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regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
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mux << lvds_mux->shift);
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}
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regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
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drm_panel_enable(imx_ldb_ch->panel);
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}
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static void
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imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *connector_state)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct drm_display_mode *mode = &crtc_state->adjusted_mode;
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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unsigned long serial_clk;
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unsigned long di_clk = mode->clock * 1000;
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int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
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u32 bus_format = imx_ldb_ch->bus_format;
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if (mode->clock > 170000) {
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dev_warn(ldb->dev,
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"%s: mode exceeds 170 MHz pixel clock\n", __func__);
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}
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if (mode->clock > 85000 && !dual) {
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dev_warn(ldb->dev,
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"%s: mode exceeds 85 MHz pixel clock\n", __func__);
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}
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if (dual) {
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serial_clk = 3500UL * mode->clock;
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imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
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imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
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} else {
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serial_clk = 7000UL * mode->clock;
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imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
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di_clk);
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}
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/* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
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if (imx_ldb_ch == &ldb->channel[0] || dual) {
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
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else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
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}
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if (imx_ldb_ch == &ldb->channel[1] || dual) {
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
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else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
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}
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if (!bus_format) {
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struct drm_connector *connector = connector_state->connector;
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struct drm_display_info *di = &connector->display_info;
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if (di->num_bus_formats)
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bus_format = di->bus_formats[0];
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}
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imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
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}
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static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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int mux, ret;
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drm_panel_disable(imx_ldb_ch->panel);
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if (imx_ldb_ch == &ldb->channel[0] || dual)
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ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
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if (imx_ldb_ch == &ldb->channel[1] || dual)
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ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
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regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
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if (dual) {
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clk_disable_unprepare(ldb->clk[0]);
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clk_disable_unprepare(ldb->clk[1]);
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}
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if (ldb->lvds_mux) {
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const struct bus_mux *lvds_mux = NULL;
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if (imx_ldb_ch == &ldb->channel[0])
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lvds_mux = &ldb->lvds_mux[0];
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else if (imx_ldb_ch == &ldb->channel[1])
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lvds_mux = &ldb->lvds_mux[1];
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regmap_read(ldb->regmap, lvds_mux->reg, &mux);
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mux &= lvds_mux->mask;
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mux >>= lvds_mux->shift;
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} else {
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mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
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}
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/* set display clock mux back to original input clock */
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ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
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if (ret)
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dev_err(ldb->dev,
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"unable to set di%d parent clock to original parent\n",
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mux);
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drm_panel_unprepare(imx_ldb_ch->panel);
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}
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static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct drm_display_info *di = &conn_state->connector->display_info;
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u32 bus_format = imx_ldb_ch->bus_format;
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/* Bus format description in DT overrides connector display info. */
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if (!bus_format && di->num_bus_formats) {
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bus_format = di->bus_formats[0];
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imx_crtc_state->bus_flags = di->bus_flags;
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} else {
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bus_format = imx_ldb_ch->bus_format;
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imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
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}
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switch (bus_format) {
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case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
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case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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break;
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default:
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return -EINVAL;
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}
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imx_crtc_state->di_hsync_pin = 2;
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imx_crtc_state->di_vsync_pin = 3;
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return 0;
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}
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static const struct drm_connector_funcs imx_ldb_connector_funcs = {
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = imx_drm_connector_destroy,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
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.get_modes = imx_ldb_connector_get_modes,
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};
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static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
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.atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
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.enable = imx_ldb_encoder_enable,
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.disable = imx_ldb_encoder_disable,
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.atomic_check = imx_ldb_encoder_atomic_check,
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};
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static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
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{
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char clkname[16];
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snprintf(clkname, sizeof(clkname), "di%d", chno);
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ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
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if (IS_ERR(ldb->clk[chno]))
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return PTR_ERR(ldb->clk[chno]);
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snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
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ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
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return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
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}
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static int imx_ldb_register(struct drm_device *drm,
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struct imx_ldb_channel *imx_ldb_ch)
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{
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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struct imx_ldb_encoder *ldb_encoder;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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int ret;
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ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder,
|
|
encoder, DRM_MODE_ENCODER_LVDS);
|
|
if (IS_ERR(ldb_encoder))
|
|
return PTR_ERR(ldb_encoder);
|
|
|
|
ldb_encoder->channel = imx_ldb_ch;
|
|
connector = &ldb_encoder->connector;
|
|
encoder = &ldb_encoder->encoder;
|
|
|
|
ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
|
|
ret = imx_ldb_get_clk(ldb, 1);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
|
|
|
|
if (imx_ldb_ch->bridge) {
|
|
ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 0);
|
|
if (ret) {
|
|
DRM_ERROR("Failed to initialize bridge with drm\n");
|
|
return ret;
|
|
}
|
|
} else {
|
|
/*
|
|
* We want to add the connector whenever there is no bridge
|
|
* that brings its own, not only when there is a panel. For
|
|
* historical reasons, the ldb driver can also work without
|
|
* a panel.
|
|
*/
|
|
drm_connector_helper_add(connector,
|
|
&imx_ldb_connector_helper_funcs);
|
|
drm_connector_init_with_ddc(drm, connector,
|
|
&imx_ldb_connector_funcs,
|
|
DRM_MODE_CONNECTOR_LVDS,
|
|
imx_ldb_ch->ddc);
|
|
drm_connector_attach_encoder(connector, encoder);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct imx_ldb_bit_mapping {
|
|
u32 bus_format;
|
|
u32 datawidth;
|
|
const char * const mapping;
|
|
};
|
|
|
|
static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
|
|
{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
|
|
{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
|
|
{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
|
|
};
|
|
|
|
static u32 of_get_bus_format(struct device *dev, struct device_node *np)
|
|
{
|
|
const char *bm;
|
|
u32 datawidth = 0;
|
|
int ret, i;
|
|
|
|
ret = of_property_read_string(np, "fsl,data-mapping", &bm);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
of_property_read_u32(np, "fsl,data-width", &datawidth);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
|
|
if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
|
|
datawidth == imx_ldb_bit_mappings[i].datawidth)
|
|
return imx_ldb_bit_mappings[i].bus_format;
|
|
}
|
|
|
|
dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
static struct bus_mux imx6q_lvds_mux[2] = {
|
|
{
|
|
.reg = IOMUXC_GPR3,
|
|
.shift = 6,
|
|
.mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
|
|
}, {
|
|
.reg = IOMUXC_GPR3,
|
|
.shift = 8,
|
|
.mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
|
|
}
|
|
};
|
|
|
|
/*
|
|
* For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
|
|
* of_match_device will walk through this list and take the first entry
|
|
* matching any of its compatible values. Therefore, the more generic
|
|
* entries (in this case fsl,imx53-ldb) need to be ordered last.
|
|
*/
|
|
static const struct of_device_id imx_ldb_dt_ids[] = {
|
|
{ .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
|
|
{ .compatible = "fsl,imx53-ldb", .data = NULL, },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
|
|
|
|
static int imx_ldb_panel_ddc(struct device *dev,
|
|
struct imx_ldb_channel *channel, struct device_node *child)
|
|
{
|
|
struct device_node *ddc_node;
|
|
const u8 *edidp;
|
|
int ret;
|
|
|
|
ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
|
|
if (ddc_node) {
|
|
channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
|
|
of_node_put(ddc_node);
|
|
if (!channel->ddc) {
|
|
dev_warn(dev, "failed to get ddc i2c adapter\n");
|
|
return -EPROBE_DEFER;
|
|
}
|
|
}
|
|
|
|
if (!channel->ddc) {
|
|
int edid_len;
|
|
|
|
/* if no DDC available, fallback to hardcoded EDID */
|
|
dev_dbg(dev, "no ddc available\n");
|
|
|
|
edidp = of_get_property(child, "edid", &edid_len);
|
|
if (edidp) {
|
|
channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
|
|
} else if (!channel->panel) {
|
|
/* fallback to display-timings node */
|
|
ret = of_get_drm_display_mode(child,
|
|
&channel->mode,
|
|
&channel->bus_flags,
|
|
OF_USE_NATIVE_MODE);
|
|
if (!ret)
|
|
channel->mode_valid = 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct drm_device *drm = data;
|
|
struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
|
|
int ret;
|
|
int i;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
struct imx_ldb_channel *channel = &imx_ldb->channel[i];
|
|
|
|
if (!channel->ldb)
|
|
break;
|
|
|
|
ret = imx_ldb_register(drm, channel);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct component_ops imx_ldb_ops = {
|
|
.bind = imx_ldb_bind,
|
|
};
|
|
|
|
static int imx_ldb_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev);
|
|
struct device_node *child;
|
|
struct imx_ldb *imx_ldb;
|
|
int dual;
|
|
int ret;
|
|
int i;
|
|
|
|
imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
|
|
if (!imx_ldb)
|
|
return -ENOMEM;
|
|
|
|
imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
|
|
if (IS_ERR(imx_ldb->regmap)) {
|
|
dev_err(dev, "failed to get parent regmap\n");
|
|
return PTR_ERR(imx_ldb->regmap);
|
|
}
|
|
|
|
/* disable LDB by resetting the control register to POR default */
|
|
regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
|
|
|
|
imx_ldb->dev = dev;
|
|
|
|
if (of_id)
|
|
imx_ldb->lvds_mux = of_id->data;
|
|
|
|
dual = of_property_read_bool(np, "fsl,dual-channel");
|
|
if (dual)
|
|
imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
|
|
|
|
/*
|
|
* There are three different possible clock mux configurations:
|
|
* i.MX53: ipu1_di0_sel, ipu1_di1_sel
|
|
* i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
|
|
* i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
|
|
* Map them all to di0_sel...di3_sel.
|
|
*/
|
|
for (i = 0; i < 4; i++) {
|
|
char clkname[16];
|
|
|
|
sprintf(clkname, "di%d_sel", i);
|
|
imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
|
|
if (IS_ERR(imx_ldb->clk_sel[i])) {
|
|
ret = PTR_ERR(imx_ldb->clk_sel[i]);
|
|
imx_ldb->clk_sel[i] = NULL;
|
|
break;
|
|
}
|
|
|
|
imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
|
|
}
|
|
if (i == 0)
|
|
return ret;
|
|
|
|
for_each_child_of_node(np, child) {
|
|
struct imx_ldb_channel *channel;
|
|
int bus_format;
|
|
|
|
ret = of_property_read_u32(child, "reg", &i);
|
|
if (ret || i < 0 || i > 1) {
|
|
ret = -EINVAL;
|
|
goto free_child;
|
|
}
|
|
|
|
if (!of_device_is_available(child))
|
|
continue;
|
|
|
|
if (dual && i > 0) {
|
|
dev_warn(dev, "dual-channel mode, ignoring second output\n");
|
|
continue;
|
|
}
|
|
|
|
channel = &imx_ldb->channel[i];
|
|
channel->ldb = imx_ldb;
|
|
channel->chno = i;
|
|
|
|
/*
|
|
* The output port is port@4 with an external 4-port mux or
|
|
* port@2 with the internal 2-port mux.
|
|
*/
|
|
ret = drm_of_find_panel_or_bridge(child,
|
|
imx_ldb->lvds_mux ? 4 : 2, 0,
|
|
&channel->panel, &channel->bridge);
|
|
if (ret && ret != -ENODEV)
|
|
goto free_child;
|
|
|
|
/* panel ddc only if there is no bridge */
|
|
if (!channel->bridge) {
|
|
ret = imx_ldb_panel_ddc(dev, channel, child);
|
|
if (ret)
|
|
goto free_child;
|
|
}
|
|
|
|
bus_format = of_get_bus_format(dev, child);
|
|
if (bus_format == -EINVAL) {
|
|
/*
|
|
* If no bus format was specified in the device tree,
|
|
* we can still get it from the connected panel later.
|
|
*/
|
|
if (channel->panel && channel->panel->funcs &&
|
|
channel->panel->funcs->get_modes)
|
|
bus_format = 0;
|
|
}
|
|
if (bus_format < 0) {
|
|
dev_err(dev, "could not determine data mapping: %d\n",
|
|
bus_format);
|
|
ret = bus_format;
|
|
goto free_child;
|
|
}
|
|
channel->bus_format = bus_format;
|
|
channel->child = child;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, imx_ldb);
|
|
|
|
return component_add(&pdev->dev, &imx_ldb_ops);
|
|
|
|
free_child:
|
|
of_node_put(child);
|
|
return ret;
|
|
}
|
|
|
|
static int imx_ldb_remove(struct platform_device *pdev)
|
|
{
|
|
struct imx_ldb *imx_ldb = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
struct imx_ldb_channel *channel = &imx_ldb->channel[i];
|
|
|
|
kfree(channel->edid);
|
|
i2c_put_adapter(channel->ddc);
|
|
}
|
|
|
|
component_del(&pdev->dev, &imx_ldb_ops);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver imx_ldb_driver = {
|
|
.probe = imx_ldb_probe,
|
|
.remove = imx_ldb_remove,
|
|
.driver = {
|
|
.of_match_table = imx_ldb_dt_ids,
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(imx_ldb_driver);
|
|
|
|
MODULE_DESCRIPTION("i.MX LVDS driver");
|
|
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|