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1dfbec3905
Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399. But dues to the carelessly copying from RK3036 when the RK3399 bringing up, the refdiv == 6, it will increase the lock time, and it is not an optimal configuration. Let's fix them for the lock time and jitter are lower: 800 MHz: - FVCO == 2.4 GHz, revdiv == 1. 1 GHz: - FVCO == 3 GHz, revdiv == 1. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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.. | ||
clk-cpu.c | ||
clk-ddr.c | ||
clk-inverter.c | ||
clk-mmc-phase.c | ||
clk-pll.c | ||
clk-rk3036.c | ||
clk-rk3188.c | ||
clk-rk3228.c | ||
clk-rk3288.c | ||
clk-rk3368.c | ||
clk-rk3399.c | ||
clk-rockchip.c | ||
clk.c | ||
clk.h | ||
Makefile | ||
softrst.c |