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519f64bf15
because of summer time holidays/vacations. The biggest change in the diffstat is in the Qualcomm clk driver, where they got support for CPUs and handful of SoCs. After that, the at91 driver got a major rewrite for newer DT bindings that should make things easier going forward and the TI code moved to a clockdomain based design. The long tail is mostly small driver updates for newer clks and some simpler SoC clock drivers such as the Hisilicon and imx support. In the core framework, we only have two small changes this time. One is a new clk API to get all clks for a device with the bulk clk APIs. This allows drivers that don't care about doing anything besides turning on all the clks to just clk_get() them all and turn them on. The other change is the beginning of a way to support save and restore of clk settings in the clk framework. TI is the only user right now, but we will want to expand upon this design in the future to support more save and restore of clk registers. At least this gets us started and works well enough for one SoC, but there's more work in the future. Core: - clk_bulk_get_all() API and friends to get all the clks for a device - Basic clk state save/restore hooks New Drivers: - Renesas RZ/A2 (R7S9210) SoC, including early clocks - Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs - Rensas RZ/G2M (r8a774a1) SoC - Qualcomm Krait CPU clk support - Qualcomm QCS404 GCC support - Qualcomm SDM660 GCC support - Qualcomm SDM845 camera clock controller - Ingenic jz4725b CGU - Hisilicon 3670 SoC support - TI SCI clks on K3 SoCs - iMX6 MMDC clks - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs Updates: - Rework at91 PMC clock driver for new DT bindings - Nvidia Tegra clk driver MBIST workaround fix - S2RAM support for Marvell mvebu periph clks - Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 - Add support for CMT timer clocks on R-Car V3H - Add support for SHDI and various timer clocks on R-Car V3M - Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs - Amlogic clk-pll driver improvements and updates - Amlogic axg audio controller system clocks - Register Amlogic meson8b clock controller early - Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N - Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers - Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC - Remove obsoleted Exynos4212 ISP clock definitions - Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design - TI RTC+DDR sleep mode support for clock save/restore - Allwinner A64 display engine support and fixes - Allwinner A83t display engine support and fixes -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlvY4ysRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVaDBAA3Wv/rsCn4FJ2ZgIWYWQqr69lAWDcBVVe 4nNbFqzEmRoml8e+XOfVFwnbsai4B5ALVxyMnRlkDyxQ5TFQtF957U12Pf8upPa5 R447YBt4tw40NCj8u5KNAaBmYYHdmXXDvsBPXyQn+1iy/9R8Is8AcDmv+D2ucuJF PPBXOwb+2CstUQhuwlXyvsAw/tqq/rJDVyAZVJUoqXJwlNMjr76V0m0ZXHN6NcyC F2SfnzIO4srRteTeKXVFcMU/3uHC3zofEfammSJjGZkk4WHULuPpkD17RMEyBul1 Ju1S1nzGiKvYME/mmbIcRPNcpry65EVo/wn6IjAcG2m4GaWSq3F6qIttnoc6dnra R2VylIEy7HnNcAf8fkQdkd/l+h/TDp3iVrXg0p/rRxRk4Jlc86n2PWO6jtsZv4S+ NySeRhTb51KrTl72J76LP+dfDWdbeZfkAqr0Qx6QM04OznVYSTHlnQaeM1Nx2SZR 5+k126NdxDp7xgoJNfq18wzufrlefjuRTg2Kck1YuFuhV4Fjmq7ZC81bSSaakYPh /t073TcSZ+VfEYP5hVsl/pjMdFzHcj8pbavhs0UNIYLQNXe494Bm9PyYJOzQKnwz Zpbf7V6eplh8J1I03VI8RHviNp340iv2hhz9vp4mNP1vIhgdNiz7R2gn5sLSoFt+ vei0J0vEzCA= =V5aK -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time it looks like a quieter release cycle in the clk tree. I guess that's because of summer time holidays/vacations. The biggest change in the diffstat is in the Qualcomm clk driver, where they got support for CPUs and handful of SoCs. After that, the at91 driver got a major rewrite for newer DT bindings that should make things easier going forward and the TI code moved to a clockdomain based design. The long tail is mostly small driver updates for newer clks and some simpler SoC clock drivers such as the Hisilicon and imx support. In the core framework, we only have two small changes this time. One is a new clk API to get all clks for a device with the bulk clk APIs. This allows drivers that don't care about doing anything besides turning on all the clks to just clk_get() them all and turn them on. The other change is the beginning of a way to support save and restore of clk settings in the clk framework. TI is the only user right now, but we will want to expand upon this design in the future to support more save and restore of clk registers. At least this gets us started and works well enough for one SoC, but there's more work in the future. Core: - clk_bulk_get_all() API and friends to get all the clks for a device - Basic clk state save/restore hooks New Drivers: - Renesas RZ/A2 (R7S9210) SoC, including early clocks - Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs - Rensas RZ/G2M (r8a774a1) SoC - Qualcomm Krait CPU clk support - Qualcomm QCS404 GCC support - Qualcomm SDM660 GCC support - Qualcomm SDM845 camera clock controller - Ingenic jz4725b CGU - Hisilicon 3670 SoC support - TI SCI clks on K3 SoCs - iMX6 MMDC clks - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs Updates: - Rework at91 PMC clock driver for new DT bindings - Nvidia Tegra clk driver MBIST workaround fix - S2RAM support for Marvell mvebu periph clks - Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 - Add support for CMT timer clocks on R-Car V3H - Add support for SHDI and various timer clocks on R-Car V3M - Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs - Amlogic clk-pll driver improvements and updates - Amlogic axg audio controller system clocks - Register Amlogic meson8b clock controller early - Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N - Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers - Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC - Remove obsoleted Exynos4212 ISP clock definitions - Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design - TI RTC+DDR sleep mode support for clock save/restore - Allwinner A64 display engine support and fixes - Allwinner A83t display engine support and fixes" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (186 commits) clk: qcom: Remove unused arrays in SDM845 GCC clk: fixed-rate: fix of_node_get-put imbalance clk: s2mps11: Add used attribute to s2mps11_dt_match clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock ...
520 lines
12 KiB
C
520 lines
12 KiB
C
/*
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* TI clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/ti.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/list.h>
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#include <linux/regmap.h>
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#include <linux/memblock.h>
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#include <linux/device.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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struct ti_clk_ll_ops *ti_clk_ll_ops;
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static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
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struct ti_clk_features ti_clk_features;
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struct clk_iomap {
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struct regmap *regmap;
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void __iomem *mem;
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};
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static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
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static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg)
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{
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struct clk_iomap *io = clk_memmaps[reg->index];
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if (reg->ptr)
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writel_relaxed(val, reg->ptr);
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else if (io->regmap)
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regmap_write(io->regmap, reg->offset, val);
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else
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writel_relaxed(val, io->mem + reg->offset);
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}
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static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr)
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{
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u32 v;
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v = readl_relaxed(ptr);
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v &= ~mask;
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v |= val;
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writel_relaxed(v, ptr);
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}
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static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg)
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{
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struct clk_iomap *io = clk_memmaps[reg->index];
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if (reg->ptr) {
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_clk_rmw(val, mask, reg->ptr);
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} else if (io->regmap) {
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regmap_update_bits(io->regmap, reg->offset, mask, val);
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} else {
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_clk_rmw(val, mask, io->mem + reg->offset);
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}
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}
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static u32 clk_memmap_readl(const struct clk_omap_reg *reg)
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{
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u32 val;
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struct clk_iomap *io = clk_memmaps[reg->index];
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if (reg->ptr)
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val = readl_relaxed(reg->ptr);
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else if (io->regmap)
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regmap_read(io->regmap, reg->offset, &val);
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else
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val = readl_relaxed(io->mem + reg->offset);
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return val;
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}
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/**
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* ti_clk_setup_ll_ops - setup low level clock operations
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* @ops: low level clock ops descriptor
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*
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* Sets up low level clock operations for TI clock driver. This is used
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* to provide various callbacks for the clock driver towards platform
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* specific code. Returns 0 on success, -EBUSY if ll_ops have been
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* registered already.
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*/
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int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
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{
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if (ti_clk_ll_ops) {
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pr_err("Attempt to register ll_ops multiple times.\n");
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return -EBUSY;
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}
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ti_clk_ll_ops = ops;
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ops->clk_readl = clk_memmap_readl;
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ops->clk_writel = clk_memmap_writel;
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ops->clk_rmw = clk_memmap_rmw;
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return 0;
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}
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/**
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* ti_dt_clocks_register - register DT alias clocks during boot
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* @oclks: list of clocks to register
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*
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* Register alias or non-standard DT clock entries during boot. By
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* default, DT clocks are found based on their node name. If any
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* additional con-id / dev-id -> clock mapping is required, use this
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* function to list these.
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*/
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void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
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{
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struct ti_dt_clk *c;
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struct device_node *node, *parent;
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struct clk *clk;
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struct of_phandle_args clkspec;
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char buf[64];
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char *ptr;
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char *tags[2];
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int i;
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int num_args;
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int ret;
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static bool clkctrl_nodes_missing;
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static bool has_clkctrl_data;
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static bool compat_mode;
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compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
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for (c = oclks; c->node_name != NULL; c++) {
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strcpy(buf, c->node_name);
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ptr = buf;
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for (i = 0; i < 2; i++)
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tags[i] = NULL;
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num_args = 0;
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while (*ptr) {
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if (*ptr == ':') {
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if (num_args >= 2) {
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pr_warn("Bad number of tags on %s\n",
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c->node_name);
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return;
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}
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tags[num_args++] = ptr + 1;
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*ptr = 0;
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}
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ptr++;
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}
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if (num_args && clkctrl_nodes_missing)
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continue;
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node = of_find_node_by_name(NULL, buf);
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if (num_args && compat_mode) {
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parent = node;
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node = of_get_child_by_name(parent, "clk");
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of_node_put(parent);
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}
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clkspec.np = node;
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clkspec.args_count = num_args;
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for (i = 0; i < num_args; i++) {
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ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
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if (ret) {
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pr_warn("Bad tag in %s at %d: %s\n",
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c->node_name, i, tags[i]);
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of_node_put(node);
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return;
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}
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}
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(node);
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if (!IS_ERR(clk)) {
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c->lk.clk = clk;
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clkdev_add(&c->lk);
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} else {
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if (num_args && !has_clkctrl_data) {
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if (of_find_compatible_node(NULL, NULL,
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"ti,clkctrl")) {
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has_clkctrl_data = true;
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} else {
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clkctrl_nodes_missing = true;
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pr_warn("missing clkctrl nodes, please update your dts.\n");
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continue;
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}
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}
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pr_warn("failed to lookup clock node %s, ret=%ld\n",
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c->node_name, PTR_ERR(clk));
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}
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}
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}
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struct clk_init_item {
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struct device_node *node;
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void *user;
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ti_of_clk_init_cb_t func;
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struct list_head link;
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};
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static LIST_HEAD(retry_list);
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/**
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* ti_clk_retry_init - retries a failed clock init at later phase
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* @node: device not for the clock
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* @user: user data pointer
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* @func: init function to be called for the clock
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*
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* Adds a failed clock init to the retry list. The retry list is parsed
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* once all the other clocks have been initialized.
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*/
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int __init ti_clk_retry_init(struct device_node *node, void *user,
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ti_of_clk_init_cb_t func)
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{
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struct clk_init_item *retry;
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pr_debug("%pOFn: adding to retry list...\n", node);
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retry = kzalloc(sizeof(*retry), GFP_KERNEL);
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if (!retry)
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return -ENOMEM;
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retry->node = node;
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retry->func = func;
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retry->user = user;
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list_add(&retry->link, &retry_list);
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return 0;
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}
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/**
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* ti_clk_get_reg_addr - get register address for a clock register
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* @node: device node for the clock
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* @index: register index from the clock node
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* @reg: pointer to target register struct
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*
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* Builds clock register address from device tree information, and returns
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* the data via the provided output pointer @reg. Returns 0 on success,
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* negative error value on failure.
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*/
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int ti_clk_get_reg_addr(struct device_node *node, int index,
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struct clk_omap_reg *reg)
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{
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u32 val;
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int i;
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for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
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if (clocks_node_ptr[i] == node->parent)
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break;
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}
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if (i == CLK_MAX_MEMMAPS) {
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pr_err("clk-provider not found for %pOFn!\n", node);
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return -ENOENT;
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}
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reg->index = i;
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if (of_property_read_u32_index(node, "reg", index, &val)) {
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pr_err("%pOFn must have reg[%d]!\n", node, index);
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return -EINVAL;
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}
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reg->offset = val;
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reg->ptr = NULL;
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return 0;
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}
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void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
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{
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u32 latch;
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if (shift < 0)
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return;
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latch = 1 << shift;
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ti_clk_ll_ops->clk_rmw(latch, latch, reg);
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ti_clk_ll_ops->clk_rmw(0, latch, reg);
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ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */
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}
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/**
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* omap2_clk_provider_init - init master clock provider
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* @parent: master node
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* @index: internal index for clk_reg_ops
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* @syscon: syscon regmap pointer for accessing clock registers
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* @mem: iomem pointer for the clock provider memory area, only used if
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* syscon is not provided
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*
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* Initializes a master clock IP block. This basically sets up the
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* mapping from clocks node to the memory map index. All the clocks
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* are then initialized through the common of_clk_init call, and the
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* clocks will access their memory maps based on the node layout.
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* Returns 0 in success.
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*/
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int __init omap2_clk_provider_init(struct device_node *parent, int index,
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struct regmap *syscon, void __iomem *mem)
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{
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struct device_node *clocks;
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struct clk_iomap *io;
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/* get clocks for this parent */
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clocks = of_get_child_by_name(parent, "clocks");
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if (!clocks) {
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pr_err("%pOFn missing 'clocks' child node.\n", parent);
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return -EINVAL;
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}
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/* add clocks node info */
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clocks_node_ptr[index] = clocks;
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io = kzalloc(sizeof(*io), GFP_KERNEL);
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if (!io)
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return -ENOMEM;
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io->regmap = syscon;
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io->mem = mem;
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clk_memmaps[index] = io;
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return 0;
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}
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/**
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* omap2_clk_legacy_provider_init - initialize a legacy clock provider
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* @index: index for the clock provider
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* @mem: iomem pointer for the clock provider memory area
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*
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* Initializes a legacy clock provider memory mapping.
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*/
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void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
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{
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struct clk_iomap *io;
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io = memblock_alloc(sizeof(*io), SMP_CACHE_BYTES);
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io->mem = mem;
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clk_memmaps[index] = io;
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}
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/**
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* ti_dt_clk_init_retry_clks - init clocks from the retry list
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*
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|
* Initializes any clocks that have failed to initialize before,
|
|
* reasons being missing parent node(s) during earlier init. This
|
|
* typically happens only for DPLLs which need to have both of their
|
|
* parent clocks ready during init.
|
|
*/
|
|
void ti_dt_clk_init_retry_clks(void)
|
|
{
|
|
struct clk_init_item *retry;
|
|
struct clk_init_item *tmp;
|
|
int retries = 5;
|
|
|
|
while (!list_empty(&retry_list) && retries) {
|
|
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
|
|
pr_debug("retry-init: %pOFn\n", retry->node);
|
|
retry->func(retry->user, retry->node);
|
|
list_del(&retry->link);
|
|
kfree(retry);
|
|
}
|
|
retries--;
|
|
}
|
|
}
|
|
|
|
static const struct of_device_id simple_clk_match_table[] __initconst = {
|
|
{ .compatible = "fixed-clock" },
|
|
{ .compatible = "fixed-factor-clock" },
|
|
{ }
|
|
};
|
|
|
|
/**
|
|
* ti_clk_add_aliases - setup clock aliases
|
|
*
|
|
* Sets up any missing clock aliases. No return value.
|
|
*/
|
|
void __init ti_clk_add_aliases(void)
|
|
{
|
|
struct device_node *np;
|
|
struct clk *clk;
|
|
|
|
for_each_matching_node(np, simple_clk_match_table) {
|
|
struct of_phandle_args clkspec;
|
|
|
|
clkspec.np = np;
|
|
clk = of_clk_get_from_provider(&clkspec);
|
|
|
|
ti_clk_add_alias(NULL, clk, np->name);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ti_clk_setup_features - setup clock features flags
|
|
* @features: features definition to use
|
|
*
|
|
* Initializes the clock driver features flags based on platform
|
|
* provided data. No return value.
|
|
*/
|
|
void __init ti_clk_setup_features(struct ti_clk_features *features)
|
|
{
|
|
memcpy(&ti_clk_features, features, sizeof(*features));
|
|
}
|
|
|
|
/**
|
|
* ti_clk_get_features - get clock driver features flags
|
|
*
|
|
* Get TI clock driver features description. Returns a pointer
|
|
* to the current feature setup.
|
|
*/
|
|
const struct ti_clk_features *ti_clk_get_features(void)
|
|
{
|
|
return &ti_clk_features;
|
|
}
|
|
|
|
/**
|
|
* omap2_clk_enable_init_clocks - prepare & enable a list of clocks
|
|
* @clk_names: ptr to an array of strings of clock names to enable
|
|
* @num_clocks: number of clock names in @clk_names
|
|
*
|
|
* Prepare and enable a list of clocks, named by @clk_names. No
|
|
* return value. XXX Deprecated; only needed until these clocks are
|
|
* properly claimed and enabled by the drivers or core code that uses
|
|
* them. XXX What code disables & calls clk_put on these clocks?
|
|
*/
|
|
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
|
|
{
|
|
struct clk *init_clk;
|
|
int i;
|
|
|
|
for (i = 0; i < num_clocks; i++) {
|
|
init_clk = clk_get(NULL, clk_names[i]);
|
|
if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
|
|
clk_names[i]))
|
|
continue;
|
|
clk_prepare_enable(init_clk);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ti_clk_add_alias - add a clock alias for a TI clock
|
|
* @dev: device alias for this clock
|
|
* @clk: clock handle to create alias for
|
|
* @con: connection ID for this clock
|
|
*
|
|
* Creates a clock alias for a TI clock. Allocates the clock lookup entry
|
|
* and assigns the data to it. Returns 0 if successful, negative error
|
|
* value otherwise.
|
|
*/
|
|
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
|
|
{
|
|
struct clk_lookup *cl;
|
|
|
|
if (!clk)
|
|
return 0;
|
|
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
|
|
if (!cl)
|
|
return -ENOMEM;
|
|
|
|
if (dev)
|
|
cl->dev_id = dev_name(dev);
|
|
cl->con_id = con;
|
|
cl->clk = clk;
|
|
|
|
clkdev_add(cl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ti_clk_register - register a TI clock to the common clock framework
|
|
* @dev: device for this clock
|
|
* @hw: hardware clock handle
|
|
* @con: connection ID for this clock
|
|
*
|
|
* Registers a TI clock to the common clock framework, and adds a clock
|
|
* alias for it. Returns a handle to the registered clock if successful,
|
|
* ERR_PTR value in failure.
|
|
*/
|
|
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
|
|
const char *con)
|
|
{
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
clk = clk_register(dev, hw);
|
|
if (IS_ERR(clk))
|
|
return clk;
|
|
|
|
ret = ti_clk_add_alias(dev, clk, con);
|
|
if (ret) {
|
|
clk_unregister(clk);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return clk;
|
|
}
|