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https://mirrors.bfsu.edu.cn/git/linux.git
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278 lines
7.7 KiB
C
278 lines
7.7 KiB
C
/*
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* Copyright 2009 Ben Skeggs
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* Copyright 2008 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_fbcon.h"
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int
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nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
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{
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struct nouveau_fbdev *nfbdev = info->par;
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struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
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struct nouveau_channel *chan = drm->channel;
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int ret;
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ret = RING_SPACE(chan, 4);
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if (ret)
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return ret;
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BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
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OUT_RING(chan, (region->sy << 16) | region->sx);
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OUT_RING(chan, (region->dy << 16) | region->dx);
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OUT_RING(chan, (region->height << 16) | region->width);
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FIRE_RING(chan);
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return 0;
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}
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int
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nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
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{
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struct nouveau_fbdev *nfbdev = info->par;
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struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
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struct nouveau_channel *chan = drm->channel;
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int ret;
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ret = RING_SPACE(chan, 7);
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if (ret)
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return ret;
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BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
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OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
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BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
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if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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info->fix.visual == FB_VISUAL_DIRECTCOLOR)
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OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
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else
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OUT_RING(chan, rect->color);
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BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
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OUT_RING(chan, (rect->dx << 16) | rect->dy);
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OUT_RING(chan, (rect->width << 16) | rect->height);
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FIRE_RING(chan);
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return 0;
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}
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int
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nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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struct nouveau_fbdev *nfbdev = info->par;
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struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
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struct nouveau_channel *chan = drm->channel;
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uint32_t fg;
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uint32_t bg;
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uint32_t dsize;
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uint32_t *data = (uint32_t *)image->data;
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int ret;
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if (image->depth != 1)
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return -ENODEV;
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ret = RING_SPACE(chan, 8);
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if (ret)
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return ret;
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if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
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fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
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bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
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} else {
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fg = image->fg_color;
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bg = image->bg_color;
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}
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BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
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OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
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OUT_RING(chan, ((image->dy + image->height) << 16) |
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((image->dx + image->width) & 0xffff));
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OUT_RING(chan, bg);
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OUT_RING(chan, fg);
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OUT_RING(chan, (image->height << 16) | ALIGN(image->width, 8));
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OUT_RING(chan, (image->height << 16) | image->width);
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OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
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dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
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while (dsize) {
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int iter_len = dsize > 128 ? 128 : dsize;
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ret = RING_SPACE(chan, iter_len + 1);
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if (ret)
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return ret;
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BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
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OUT_RINGp(chan, data, iter_len);
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data += iter_len;
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dsize -= iter_len;
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}
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FIRE_RING(chan);
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return 0;
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}
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int
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nv04_fbcon_accel_init(struct fb_info *info)
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{
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struct nouveau_fbdev *nfbdev = info->par;
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struct drm_device *dev = nfbdev->helper.dev;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_channel *chan = drm->channel;
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struct nvif_device *device = &drm->client.device;
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int surface_fmt, pattern_fmt, rect_fmt;
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int ret;
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switch (info->var.bits_per_pixel) {
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case 8:
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surface_fmt = 1;
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pattern_fmt = 3;
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rect_fmt = 3;
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break;
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case 16:
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surface_fmt = 4;
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pattern_fmt = 1;
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rect_fmt = 1;
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break;
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case 32:
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switch (info->var.transp.length) {
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case 0: /* depth 24 */
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case 8: /* depth 32 */
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break;
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default:
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return -EINVAL;
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}
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surface_fmt = 6;
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pattern_fmt = 3;
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rect_fmt = 3;
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break;
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default:
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return -EINVAL;
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}
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ret = nvif_object_init(&chan->user, 0x0062,
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device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
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0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
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if (ret)
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return ret;
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ret = nvif_object_init(&chan->user, 0x0019, 0x0019, NULL, 0,
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&nfbdev->clip);
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if (ret)
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return ret;
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ret = nvif_object_init(&chan->user, 0x0043, 0x0043, NULL, 0,
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&nfbdev->rop);
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if (ret)
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return ret;
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ret = nvif_object_init(&chan->user, 0x0044, 0x0044, NULL, 0,
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&nfbdev->patt);
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if (ret)
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return ret;
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ret = nvif_object_init(&chan->user, 0x004a, 0x004a, NULL, 0,
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&nfbdev->gdi);
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if (ret)
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return ret;
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ret = nvif_object_init(&chan->user, 0x005f,
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device->info.chipset >= 0x11 ? 0x009f : 0x005f,
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NULL, 0, &nfbdev->blit);
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if (ret)
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return ret;
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if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
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nouveau_fbcon_gpu_lockup(info);
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return 0;
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}
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
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OUT_RING(chan, nfbdev->surf2d.handle);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
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OUT_RING(chan, chan->vram.handle);
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OUT_RING(chan, chan->vram.handle);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
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OUT_RING(chan, surface_fmt);
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OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
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OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
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OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
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OUT_RING(chan, nfbdev->rop.handle);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
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OUT_RING(chan, 0x55);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
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OUT_RING(chan, nfbdev->patt.handle);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
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OUT_RING(chan, pattern_fmt);
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#ifdef __BIG_ENDIAN
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OUT_RING(chan, 2);
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#else
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OUT_RING(chan, 1);
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#endif
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OUT_RING(chan, 0);
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OUT_RING(chan, 1);
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OUT_RING(chan, ~0);
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OUT_RING(chan, ~0);
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OUT_RING(chan, ~0);
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OUT_RING(chan, ~0);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
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OUT_RING(chan, nfbdev->clip.handle);
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BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
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OUT_RING(chan, 0);
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OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
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OUT_RING(chan, nfbdev->blit.handle);
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BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
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OUT_RING(chan, nfbdev->surf2d.handle);
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BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
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OUT_RING(chan, 3);
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if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
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BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
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OUT_RING(chan, 0);
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OUT_RING(chan, 1);
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OUT_RING(chan, 2);
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}
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BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
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OUT_RING(chan, nfbdev->gdi.handle);
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BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
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OUT_RING(chan, nfbdev->surf2d.handle);
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BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
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OUT_RING(chan, nfbdev->patt.handle);
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OUT_RING(chan, nfbdev->rop.handle);
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BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
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OUT_RING(chan, 1);
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BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
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OUT_RING(chan, rect_fmt);
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BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
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OUT_RING(chan, 3);
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FIRE_RING(chan);
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return 0;
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}
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