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1c101da8b9
By default, even if PROT_MTE is set on a memory range, there is no tag check fault reporting (SIGSEGV). Introduce a set of option to the exiting prctl(PR_SET_TAGGED_ADDR_CTRL) to allow user control of the tag check fault mode: PR_MTE_TCF_NONE - no reporting (default) PR_MTE_TCF_SYNC - synchronous tag check fault reporting PR_MTE_TCF_ASYNC - asynchronous tag check fault reporting These options translate into the corresponding SCTLR_EL1.TCF0 bitfield, context-switched by the kernel. Note that the kernel accesses to the user address space (e.g. read() system call) are not checked if the user thread tag checking mode is PR_MTE_TCF_NONE or PR_MTE_TCF_ASYNC. If the tag checking mode is PR_MTE_TCF_SYNC, the kernel makes a best effort to check its user address accesses, however it cannot always guarantee it. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org>
139 lines
2.9 KiB
C
139 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 ARM Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/mm.h>
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#include <linux/prctl.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/thread_info.h>
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#include <asm/cpufeature.h>
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#include <asm/mte.h>
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#include <asm/sysreg.h>
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void mte_sync_tags(pte_t *ptep, pte_t pte)
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{
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struct page *page = pte_page(pte);
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long i, nr_pages = compound_nr(page);
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/* if PG_mte_tagged is set, tags have already been initialised */
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for (i = 0; i < nr_pages; i++, page++) {
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if (!test_and_set_bit(PG_mte_tagged, &page->flags))
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mte_clear_page_tags(page_address(page));
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}
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}
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int memcmp_pages(struct page *page1, struct page *page2)
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{
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char *addr1, *addr2;
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int ret;
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addr1 = page_address(page1);
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addr2 = page_address(page2);
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ret = memcmp(addr1, addr2, PAGE_SIZE);
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if (!system_supports_mte() || ret)
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return ret;
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/*
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* If the page content is identical but at least one of the pages is
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* tagged, return non-zero to avoid KSM merging. If only one of the
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* pages is tagged, set_pte_at() may zero or change the tags of the
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* other page via mte_sync_tags().
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*/
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if (test_bit(PG_mte_tagged, &page1->flags) ||
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test_bit(PG_mte_tagged, &page2->flags))
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return addr1 != addr2;
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return ret;
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}
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static void update_sctlr_el1_tcf0(u64 tcf0)
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{
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/* ISB required for the kernel uaccess routines */
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF0_MASK, tcf0);
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isb();
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}
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static void set_sctlr_el1_tcf0(u64 tcf0)
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{
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/*
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* mte_thread_switch() checks current->thread.sctlr_tcf0 as an
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* optimisation. Disable preemption so that it does not see
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* the variable update before the SCTLR_EL1.TCF0 one.
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*/
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preempt_disable();
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current->thread.sctlr_tcf0 = tcf0;
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update_sctlr_el1_tcf0(tcf0);
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preempt_enable();
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}
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void flush_mte_state(void)
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{
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if (!system_supports_mte())
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return;
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/* clear any pending asynchronous tag fault */
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dsb(ish);
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write_sysreg_s(0, SYS_TFSRE0_EL1);
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clear_thread_flag(TIF_MTE_ASYNC_FAULT);
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/* disable tag checking */
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set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE);
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}
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void mte_thread_switch(struct task_struct *next)
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{
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if (!system_supports_mte())
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return;
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/* avoid expensive SCTLR_EL1 accesses if no change */
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if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0)
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update_sctlr_el1_tcf0(next->thread.sctlr_tcf0);
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}
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long set_mte_ctrl(unsigned long arg)
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{
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u64 tcf0;
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if (!system_supports_mte())
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return 0;
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switch (arg & PR_MTE_TCF_MASK) {
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case PR_MTE_TCF_NONE:
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tcf0 = SCTLR_EL1_TCF0_NONE;
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break;
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case PR_MTE_TCF_SYNC:
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tcf0 = SCTLR_EL1_TCF0_SYNC;
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break;
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case PR_MTE_TCF_ASYNC:
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tcf0 = SCTLR_EL1_TCF0_ASYNC;
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break;
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default:
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return -EINVAL;
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}
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set_sctlr_el1_tcf0(tcf0);
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return 0;
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}
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long get_mte_ctrl(void)
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{
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if (!system_supports_mte())
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return 0;
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switch (current->thread.sctlr_tcf0) {
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case SCTLR_EL1_TCF0_NONE:
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return PR_MTE_TCF_NONE;
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case SCTLR_EL1_TCF0_SYNC:
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return PR_MTE_TCF_SYNC;
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case SCTLR_EL1_TCF0_ASYNC:
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return PR_MTE_TCF_ASYNC;
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}
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return 0;
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}
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