mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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6d68d9cba1
- Remove the "log-like" parts, following the same logic as the previous commit - Unify format - Add missing major contributors, including myself - Sort entries in order of first contribution (Creative comes last for optical reasons; they don't appear to have directly contributed anyway) Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de> Link: https://lore.kernel.org/r/20230715160839.326978-2-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai <tiwai@suse.de>
726 lines
19 KiB
C
726 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
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* Lee Revell <rlrevell@joe-job.com>
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* James Courtier-Dutton <James@superbug.co.uk>
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* Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
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* Creative Labs, Inc.
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*
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* Routines for control of EMU10K1 chips
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*/
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#include <linux/time.h>
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#include <sound/core.h>
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#include <sound/emu10k1.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include "p17v.h"
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static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg)
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{
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if (snd_BUG_ON(!emu))
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return false;
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if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK)
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: (0xffff0000 & ~PTR_ADDRESS_MASK))))
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return false;
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if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK))
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return false;
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return true;
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}
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unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn)
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{
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unsigned long flags;
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unsigned int regptr, val;
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unsigned int mask;
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regptr = (reg << 16) | chn;
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if (!check_ptr_reg(emu, regptr))
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return 0;
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(regptr, emu->port + PTR);
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val = inl(emu->port + DATA);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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if (reg & 0xff000000) {
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unsigned char size, offset;
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size = (reg >> 24) & 0x3f;
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offset = (reg >> 16) & 0x1f;
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mask = (1 << size) - 1;
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return (val >> offset) & mask;
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} else {
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return val;
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}
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}
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EXPORT_SYMBOL(snd_emu10k1_ptr_read);
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void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data)
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{
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unsigned int regptr;
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unsigned long flags;
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unsigned int mask;
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regptr = (reg << 16) | chn;
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if (!check_ptr_reg(emu, regptr))
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return;
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if (reg & 0xff000000) {
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unsigned char size, offset;
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size = (reg >> 24) & 0x3f;
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offset = (reg >> 16) & 0x1f;
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mask = (1 << size) - 1;
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if (snd_BUG_ON(data & ~mask))
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return;
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mask <<= offset;
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data <<= offset;
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(regptr, emu->port + PTR);
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data |= inl(emu->port + DATA) & ~mask;
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} else {
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(regptr, emu->port + PTR);
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}
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outl(data, emu->port + DATA);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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EXPORT_SYMBOL(snd_emu10k1_ptr_write);
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void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...)
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{
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va_list va;
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u32 addr_mask;
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unsigned long flags;
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if (snd_BUG_ON(!emu))
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return;
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if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK))
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return;
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addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16);
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va_start(va, chn);
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spin_lock_irqsave(&emu->emu_lock, flags);
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for (;;) {
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u32 data;
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u32 reg = va_arg(va, u32);
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if (reg == REGLIST_END)
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break;
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data = va_arg(va, u32);
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if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here
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continue;
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outl((reg << 16) | chn, emu->port + PTR);
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outl(data, emu->port + DATA);
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}
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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va_end(va);
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}
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EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple);
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unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu,
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unsigned int reg,
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unsigned int chn)
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{
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unsigned long flags;
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unsigned int regptr, val;
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regptr = (reg << 16) | chn;
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(regptr, emu->port + PTR2);
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val = inl(emu->port + DATA2);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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return val;
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}
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void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu,
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unsigned int reg,
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unsigned int chn,
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unsigned int data)
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{
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unsigned int regptr;
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unsigned long flags;
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regptr = (reg << 16) | chn;
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(regptr, emu->port + PTR2);
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outl(data, emu->port + DATA2);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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int snd_emu10k1_spi_write(struct snd_emu10k1 * emu,
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unsigned int data)
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{
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unsigned int reset, set;
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unsigned int reg, tmp;
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int n, result;
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int err = 0;
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/* This function is not re-entrant, so protect against it. */
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spin_lock(&emu->spi_lock);
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if (emu->card_capabilities->ca0108_chip)
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reg = P17V_SPI;
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else {
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/* For other chip types the SPI register
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* is currently unknown. */
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err = 1;
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goto spi_write_exit;
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}
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if (data > 0xffff) {
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/* Only 16bit values allowed */
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err = 1;
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goto spi_write_exit;
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}
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tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
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reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
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set = reset | 0x10000; /* Set xxx1xxxx */
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snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
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tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */
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snd_emu10k1_ptr20_write(emu, reg, 0, set | data);
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result = 1;
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/* Wait for status bit to return to 0 */
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for (n = 0; n < 100; n++) {
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udelay(10);
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tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
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if (!(tmp & 0x10000)) {
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result = 0;
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break;
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}
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}
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if (result) {
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/* Timed out */
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err = 1;
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goto spi_write_exit;
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}
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snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
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tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */
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err = 0;
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spi_write_exit:
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spin_unlock(&emu->spi_lock);
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return err;
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}
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/* The ADC does not support i2c read, so only write is implemented */
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int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu,
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u32 reg,
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u32 value)
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{
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u32 tmp;
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int timeout = 0;
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int status;
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int retry;
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int err = 0;
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if ((reg > 0x7f) || (value > 0x1ff)) {
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dev_err(emu->card->dev, "i2c_write: invalid values.\n");
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return -EINVAL;
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}
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/* This function is not re-entrant, so protect against it. */
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spin_lock(&emu->i2c_lock);
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tmp = reg << 25 | value << 16;
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/* This controls the I2C connected to the WM8775 ADC Codec */
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snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp);
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tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */
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for (retry = 0; retry < 10; retry++) {
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/* Send the data to i2c */
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tmp = 0;
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tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
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snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp);
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/* Wait till the transaction ends */
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while (1) {
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mdelay(1);
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status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0);
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timeout++;
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if ((status & I2C_A_ADC_START) == 0)
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break;
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if (timeout > 1000) {
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dev_warn(emu->card->dev,
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"emu10k1:I2C:timeout status=0x%x\n",
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status);
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break;
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}
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}
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//Read back and see if the transaction is successful
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if ((status & I2C_A_ADC_ABORT) == 0)
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break;
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}
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if (retry == 10) {
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dev_err(emu->card->dev, "Writing to ADC failed!\n");
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dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n",
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status, reg, value);
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/* dump_stack(); */
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err = -EINVAL;
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}
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spin_unlock(&emu->i2c_lock);
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return err;
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}
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static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value)
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{
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if (snd_BUG_ON(reg > 0x3f))
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return;
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reg += 0x40; /* 0x40 upwards are registers. */
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if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */
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return;
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outw(reg, emu->port + A_GPIO);
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udelay(10);
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outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
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udelay(10);
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outw(value, emu->port + A_GPIO);
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udelay(10);
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outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
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}
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void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value)
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{
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unsigned long flags;
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spin_lock_irqsave(&emu->emu_lock, flags);
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snd_emu1010_fpga_write_locked(emu, reg, value);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value)
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{
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// The higest input pin is used as the designated interrupt trigger,
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// so it needs to be masked out.
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// But note that any other input pin change will also cause an IRQ,
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// so using this function often causes an IRQ as a side effect.
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u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f;
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if (snd_BUG_ON(reg > 0x3f))
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return;
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reg += 0x40; /* 0x40 upwards are registers. */
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outw(reg, emu->port + A_GPIO);
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udelay(10);
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outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
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udelay(10);
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*value = ((inw(emu->port + A_GPIO) >> 8) & mask);
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}
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void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
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{
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unsigned long flags;
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spin_lock_irqsave(&emu->emu_lock, flags);
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snd_emu1010_fpga_read_locked(emu, reg, value);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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/* Each Destination has one and only one Source,
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* but one Source can feed any number of Destinations simultaneously.
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*/
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void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src)
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{
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unsigned long flags;
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if (snd_BUG_ON(dst & ~0x71f))
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return;
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if (snd_BUG_ON(src & ~0x71f))
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return;
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spin_lock_irqsave(&emu->emu_lock, flags);
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snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
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snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
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snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8);
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snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst)
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{
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unsigned long flags;
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u32 hi, lo;
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if (snd_BUG_ON(dst & ~0x71f))
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return 0;
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spin_lock_irqsave(&emu->emu_lock, flags);
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snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
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snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
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snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi);
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snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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return (hi << 8) | lo;
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}
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int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src)
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{
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u32 reg_lo, reg_hi, value, value2;
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switch (src) {
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case EMU_HANA_WCLOCK_HANA_SPDIF_IN:
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snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value);
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if (value & EMU_HANA_SPDIF_MODE_RX_INVALID)
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return 0;
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reg_lo = EMU_HANA_WC_SPDIF_LO;
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reg_hi = EMU_HANA_WC_SPDIF_HI;
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break;
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case EMU_HANA_WCLOCK_HANA_ADAT_IN:
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reg_lo = EMU_HANA_WC_ADAT_LO;
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reg_hi = EMU_HANA_WC_ADAT_HI;
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break;
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case EMU_HANA_WCLOCK_SYNC_BNC:
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reg_lo = EMU_HANA_WC_BNC_LO;
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reg_hi = EMU_HANA_WC_BNC_HI;
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break;
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case EMU_HANA_WCLOCK_2ND_HANA:
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reg_lo = EMU_HANA2_WC_SPDIF_LO;
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reg_hi = EMU_HANA2_WC_SPDIF_HI;
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break;
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default:
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return 0;
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}
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snd_emu1010_fpga_read(emu, reg_hi, &value);
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snd_emu1010_fpga_read(emu, reg_lo, &value2);
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// FIXME: The /4 is valid for 0404b, but contradicts all other info.
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return 0x1770000 / 4 / (((value << 5) | value2) + 1);
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}
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void snd_emu1010_update_clock(struct snd_emu10k1 *emu)
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{
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int clock;
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u32 leds;
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switch (emu->emu1010.wclock) {
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case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X:
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clock = 44100;
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leds = EMU_HANA_DOCK_LEDS_2_44K;
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break;
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case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X:
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clock = 48000;
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leds = EMU_HANA_DOCK_LEDS_2_48K;
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break;
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default:
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clock = snd_emu1010_get_raw_rate(
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emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK);
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// The raw rate reading is rather coarse (it cannot accurately
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// represent 44.1 kHz) and fluctuates slightly. Luckily, the
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// clock comes from digital inputs, which use standardized rates.
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// So we round to the closest standard rate and ignore discrepancies.
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if (clock < 46000) {
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clock = 44100;
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leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_44K;
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} else {
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clock = 48000;
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leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_48K;
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}
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break;
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}
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emu->emu1010.word_clock = clock;
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// FIXME: this should probably represent the AND of all currently
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// used sources' lock status. But we don't know how to get that ...
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leds |= EMU_HANA_DOCK_LEDS_2_LOCK;
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snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds);
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}
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void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)
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{
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unsigned long flags;
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unsigned int enable;
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spin_lock_irqsave(&emu->emu_lock, flags);
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enable = inl(emu->port + INTE) | intrenb;
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outl(enable, emu->port + INTE);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb)
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{
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unsigned long flags;
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unsigned int enable;
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spin_lock_irqsave(&emu->emu_lock, flags);
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enable = inl(emu->port + INTE) & ~intrenb;
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outl(enable, emu->port + INTE);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
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{
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unsigned long flags;
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unsigned int val;
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spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(CLIEH << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val |= 1 << (voicenum - 32);
|
|
} else {
|
|
outl(CLIEL << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val |= 1 << voicenum;
|
|
}
|
|
outl(val, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int val;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(CLIEH << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val &= ~(1 << (voicenum - 32));
|
|
} else {
|
|
outl(CLIEL << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val &= ~(1 << voicenum);
|
|
}
|
|
outl(val, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(CLIPH << 16, emu->port + PTR);
|
|
voicenum = 1 << (voicenum - 32);
|
|
} else {
|
|
outl(CLIPL << 16, emu->port + PTR);
|
|
voicenum = 1 << voicenum;
|
|
}
|
|
outl(voicenum, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int val;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(HLIEH << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val |= 1 << (voicenum - 32);
|
|
} else {
|
|
outl(HLIEL << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val |= 1 << voicenum;
|
|
}
|
|
outl(val, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int val;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(HLIEH << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val &= ~(1 << (voicenum - 32));
|
|
} else {
|
|
outl(HLIEL << 16, emu->port + PTR);
|
|
val = inl(emu->port + DATA);
|
|
val &= ~(1 << voicenum);
|
|
}
|
|
outl(val, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(HLIPH << 16, emu->port + PTR);
|
|
voicenum = 1 << (voicenum - 32);
|
|
} else {
|
|
outl(HLIPL << 16, emu->port + PTR);
|
|
voicenum = 1 << voicenum;
|
|
}
|
|
outl(voicenum, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
#if 0
|
|
void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int sol;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(SOLEH << 16, emu->port + PTR);
|
|
sol = inl(emu->port + DATA);
|
|
sol |= 1 << (voicenum - 32);
|
|
} else {
|
|
outl(SOLEL << 16, emu->port + PTR);
|
|
sol = inl(emu->port + DATA);
|
|
sol |= 1 << voicenum;
|
|
}
|
|
outl(sol, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int sol;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
if (voicenum >= 32) {
|
|
outl(SOLEH << 16, emu->port + PTR);
|
|
sol = inl(emu->port + DATA);
|
|
sol &= ~(1 << (voicenum - 32));
|
|
} else {
|
|
outl(SOLEL << 16, emu->port + PTR);
|
|
sol = inl(emu->port + DATA);
|
|
sol &= ~(1 << voicenum);
|
|
}
|
|
outl(sol, emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
#endif
|
|
|
|
void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
outl(SOLEL << 16, emu->port + PTR);
|
|
outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA);
|
|
outl(SOLEH << 16, emu->port + PTR);
|
|
outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
outl(SOLEL << 16, emu->port + PTR);
|
|
outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA);
|
|
outl(SOLEH << 16, emu->port + PTR);
|
|
outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|
|
|
|
int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices)
|
|
{
|
|
unsigned long flags;
|
|
u32 soll, solh;
|
|
int ret = -EIO;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
|
|
outl(SOLEL << 16, emu->port + PTR);
|
|
soll = inl(emu->port + DATA);
|
|
outl(SOLEH << 16, emu->port + PTR);
|
|
solh = inl(emu->port + DATA);
|
|
|
|
soll &= (u32)~voices;
|
|
solh &= (u32)(~voices >> 32);
|
|
|
|
for (int tries = 0; tries < 1000; tries++) {
|
|
const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2);
|
|
// First we wait for the third quarter of the sample cycle ...
|
|
u32 wc = inl(emu->port + WC);
|
|
u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc);
|
|
if (cc >= quart * 2 && cc < quart * 3) {
|
|
// ... and release the low voices, while the high ones are serviced.
|
|
outl(SOLEL << 16, emu->port + PTR);
|
|
outl(soll, emu->port + DATA);
|
|
// Then we wait for the first quarter of the next sample cycle ...
|
|
for (; tries < 1000; tries++) {
|
|
cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC));
|
|
if (cc < quart)
|
|
goto good;
|
|
// We will block for 10+ us with interrupts disabled. This is
|
|
// not nice at all, but necessary for reasonable reliability.
|
|
udelay(1);
|
|
}
|
|
break;
|
|
good:
|
|
// ... and release the high voices, while the low ones are serviced.
|
|
outl(SOLEH << 16, emu->port + PTR);
|
|
outl(solh, emu->port + DATA);
|
|
// Finally we verify that nothing interfered in fact.
|
|
if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) ==
|
|
((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) {
|
|
ret = 0;
|
|
} else {
|
|
ret = -EAGAIN;
|
|
}
|
|
break;
|
|
}
|
|
// Don't block for too long
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
udelay(1);
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait)
|
|
{
|
|
volatile unsigned count;
|
|
unsigned int newtime = 0, curtime;
|
|
|
|
curtime = inl(emu->port + WC) >> 6;
|
|
while (wait-- > 0) {
|
|
count = 0;
|
|
while (count++ < 16384) {
|
|
newtime = inl(emu->port + WC) >> 6;
|
|
if (newtime != curtime)
|
|
break;
|
|
}
|
|
if (count > 16384)
|
|
break;
|
|
curtime = newtime;
|
|
}
|
|
}
|
|
|
|
unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
|
|
{
|
|
struct snd_emu10k1 *emu = ac97->private_data;
|
|
unsigned long flags;
|
|
unsigned short val;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
outb(reg, emu->port + AC97ADDRESS);
|
|
val = inw(emu->port + AC97DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
return val;
|
|
}
|
|
|
|
void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data)
|
|
{
|
|
struct snd_emu10k1 *emu = ac97->private_data;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&emu->emu_lock, flags);
|
|
outb(reg, emu->port + AC97ADDRESS);
|
|
outw(data, emu->port + AC97DATA);
|
|
spin_unlock_irqrestore(&emu->emu_lock, flags);
|
|
}
|