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6a734b3720
pll0831x PLL is used in Exynos850 SoC for top-level fractional PLLs. The
code was derived from very similar pll36xx type, with next differences:
1. Lock time for pll0831x is 500*P_DIV, when for pll36xx it's 3000*P_DIV
2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require
performing PLL lock procedure (which is done in pll36xx
implementation)
3. The offset from PMS-values register to K-value register is 0x8 for
pll0831x, when for pll36xx it's 0x4
When defining pll0831x type, CON3 register offset should be provided as
a "con" parameter of PLL() macro, like this:
PLL(pll_0831x, 0, "fout_mmc_pll", "oscclk",
PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, pll0831x_26mhz_tbl),
To define PLL rates table, one can use PLL_36XX_RATE() macro, e.g.:
PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124)
as it's completely appropriate for pl0831x type and there is no sense in
duplicating that.
If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be
possible to set new rate, with next error showing in kernel log:
Could not lock PLL fout_mmc_pll
That can happen for example if bootloader clears that bit beforehand.
PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was
cleared, it's assumed it was done for a reason and it shouldn't be
possible to change that PLL's rate at all.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211008154352.19519-3-semen.protsenko@linaro.org
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
134 lines
2.8 KiB
C
134 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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*
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* Common Clock Framework support for all PLL's in Samsung platforms
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*/
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#ifndef __SAMSUNG_CLK_PLL_H
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#define __SAMSUNG_CLK_PLL_H
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enum samsung_pll_type {
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pll_2126,
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pll_3000,
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pll_35xx,
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pll_36xx,
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pll_2550,
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pll_2650,
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pll_4500,
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pll_4502,
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pll_4508,
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pll_4600,
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pll_4650,
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pll_4650c,
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pll_6552,
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pll_6552_s3c2416,
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pll_6553,
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pll_s3c2410_mpll,
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pll_s3c2410_upll,
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pll_s3c2440_mpll,
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pll_2550x,
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pll_2550xx,
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pll_2650x,
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pll_2650xx,
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pll_1450x,
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pll_1451x,
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pll_1452x,
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pll_1460x,
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pll_0822x,
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pll_0831x,
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};
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#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
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((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
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#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
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BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
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#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m + 8, _p + 2, _s, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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2 * (_m + 8), _p + 2, _s, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, _k, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s - 1, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.afc = (_afc), \
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}
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#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, _k, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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.vsel = (_vsel), \
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}
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#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m, _p, _s, _k, 10), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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.mfr = (_mfr), \
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.mrr = (_mrr), \
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.vsel = (_vsel), \
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}
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/* NOTE: Rate table should be kept sorted in descending order. */
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struct samsung_pll_rate_table {
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unsigned int rate;
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unsigned int pdiv;
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unsigned int mdiv;
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unsigned int sdiv;
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unsigned int kdiv;
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unsigned int afc;
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unsigned int mfr;
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unsigned int mrr;
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unsigned int vsel;
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};
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#endif /* __SAMSUNG_CLK_PLL_H */
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