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7029db09b2
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
parent with cpuck as seen in the following clock tree:
+----------> cpuck
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FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
while changing FRAC PLL or DIV PLL the commit implements a notifier for
mck0 which applies a safe divider to register (maximum value of the divider
which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
events.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
259 lines
6.7 KiB
C
259 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/at91.h>
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#include "pmc.h"
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static DEFINE_SPINLOCK(at91sam9n12_mck_lock);
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static const struct clk_master_characteristics mck_characteristics = {
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.output = { .min = 0, .max = 133333333 },
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.divisors = { 1, 2, 4, 3 },
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.have_div3_pres = 1,
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};
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static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
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static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
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static const struct clk_range plla_outputs[] = {
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{ .min = 745000000, .max = 800000000 },
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{ .min = 695000000, .max = 750000000 },
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{ .min = 645000000, .max = 700000000 },
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{ .min = 595000000, .max = 650000000 },
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{ .min = 545000000, .max = 600000000 },
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{ .min = 495000000, .max = 555000000 },
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{ .min = 445000000, .max = 500000000 },
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{ .min = 400000000, .max = 450000000 },
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};
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static const struct clk_pll_characteristics plla_characteristics = {
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.input = { .min = 2000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(plla_outputs),
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.output = plla_outputs,
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.icpll = plla_icpll,
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.out = plla_out,
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};
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static u8 pllb_out[] = { 0 };
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static const struct clk_range pllb_outputs[] = {
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{ .min = 30000000, .max = 100000000 },
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};
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static const struct clk_pll_characteristics pllb_characteristics = {
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.input = { .min = 2000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(pllb_outputs),
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.output = pllb_outputs,
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.out = pllb_out,
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};
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static const struct {
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char *n;
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char *p;
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u8 id;
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} at91sam9n12_systemck[] = {
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{ .n = "ddrck", .p = "masterck_div", .id = 2 },
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{ .n = "lcdck", .p = "masterck_div", .id = 3 },
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{ .n = "uhpck", .p = "usbck", .id = 6 },
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{ .n = "udpck", .p = "usbck", .id = 7 },
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{ .n = "pck0", .p = "prog0", .id = 8 },
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{ .n = "pck1", .p = "prog1", .id = 9 },
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};
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static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
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.offset = 0x10c,
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.cmd = BIT(12),
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.pid_mask = GENMASK(5, 0),
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.div_mask = GENMASK(17, 16),
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};
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struct pck {
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char *n;
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u8 id;
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};
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static const struct pck at91sam9n12_periphck[] = {
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{ .n = "pioAB_clk", .id = 2, },
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{ .n = "pioCD_clk", .id = 3, },
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{ .n = "fuse_clk", .id = 4, },
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{ .n = "usart0_clk", .id = 5, },
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{ .n = "usart1_clk", .id = 6, },
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{ .n = "usart2_clk", .id = 7, },
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{ .n = "usart3_clk", .id = 8, },
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{ .n = "twi0_clk", .id = 9, },
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{ .n = "twi1_clk", .id = 10, },
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{ .n = "mci0_clk", .id = 12, },
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{ .n = "spi0_clk", .id = 13, },
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{ .n = "spi1_clk", .id = 14, },
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{ .n = "uart0_clk", .id = 15, },
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{ .n = "uart1_clk", .id = 16, },
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{ .n = "tcb_clk", .id = 17, },
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{ .n = "pwm_clk", .id = 18, },
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{ .n = "adc_clk", .id = 19, },
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{ .n = "dma0_clk", .id = 20, },
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{ .n = "uhphs_clk", .id = 22, },
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{ .n = "udphs_clk", .id = 23, },
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{ .n = "lcdc_clk", .id = 25, },
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{ .n = "sha_clk", .id = 27, },
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{ .n = "ssc0_clk", .id = 28, },
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{ .n = "aes_clk", .id = 29, },
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{ .n = "trng_clk", .id = 30, },
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};
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static void __init at91sam9n12_pmc_setup(struct device_node *np)
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{
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struct clk_range range = CLK_RANGE(0, 0);
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const char *slck_name, *mainxtal_name;
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struct pmc_data *at91sam9n12_pmc;
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const char *parent_names[6];
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struct regmap *regmap;
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struct clk_hw *hw;
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int i;
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bool bypass;
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i = of_property_match_string(np, "clock-names", "slow_clk");
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if (i < 0)
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return;
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slck_name = of_clk_get_parent_name(np, i);
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i = of_property_match_string(np, "clock-names", "main_xtal");
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if (i < 0)
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return;
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mainxtal_name = of_clk_get_parent_name(np, i);
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regmap = device_node_to_regmap(np);
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if (IS_ERR(regmap))
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return;
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at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
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nck(at91sam9n12_systemck), 31, 0, 2);
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if (!at91sam9n12_pmc)
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return;
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hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
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50000000);
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if (IS_ERR(hw))
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goto err_free;
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
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bypass);
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if (IS_ERR(hw))
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goto err_free;
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parent_names[0] = "main_rc_osc";
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parent_names[1] = "main_osc";
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hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->chws[PMC_MAIN] = hw;
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hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
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&at91rm9200_pll_layout, &plla_characteristics);
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if (IS_ERR(hw))
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goto err_free;
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hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
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hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
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&at91rm9200_pll_layout, &pllb_characteristics);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
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parent_names[0] = slck_name;
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parent_names[1] = "mainck";
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parent_names[2] = "plladivck";
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parent_names[3] = "pllbck";
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91sam9x5_master_layout,
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&mck_characteristics,
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&at91sam9n12_mck_lock,
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CLK_SET_RATE_GATE, INT_MIN);
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if (IS_ERR(hw))
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goto err_free;
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hw = at91_clk_register_master_div(regmap, "masterck_div",
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"masterck_pres",
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&at91sam9x5_master_layout,
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&mck_characteristics,
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&at91sam9n12_mck_lock,
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CLK_SET_RATE_GATE, 0);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->chws[PMC_MCK] = hw;
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hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
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if (IS_ERR(hw))
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goto err_free;
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parent_names[0] = slck_name;
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parent_names[1] = "mainck";
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parent_names[2] = "plladivck";
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parent_names[3] = "pllbck";
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parent_names[4] = "masterck_div";
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for (i = 0; i < 2; i++) {
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char name[6];
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snprintf(name, sizeof(name), "prog%d", i);
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hw = at91_clk_register_programmable(regmap, name,
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parent_names, 5, i,
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&at91sam9x5_programmable_layout,
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NULL);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->pchws[i] = hw;
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}
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for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
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hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
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at91sam9n12_systemck[i].p,
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at91sam9n12_systemck[i].id);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
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}
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for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
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hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
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&at91sam9n12_pcr_layout,
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at91sam9n12_periphck[i].n,
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"masterck_div",
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at91sam9n12_periphck[i].id,
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&range, INT_MIN);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
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}
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of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
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return;
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err_free:
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kfree(at91sam9n12_pmc);
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}
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/*
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* The TCB is used as the clocksource so its clock is needed early. This means
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* this can't be a platform driver.
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*/
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CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
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