Mark James 1ac31de744 ARM: socfpga: dts: fix spi1 interrupt ... The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1 Trying to use the master without this change results in the kernel boot process waiting forever for an interrupt that will never occur while attempting to probe any slave devices configured in the device tree as being under SPI master 1. The change works for the Cyclone V, and according to the Arria 5 handbook should be good there too. Signed-off-by: Mark James <maj@jamers.net> Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>		2015-03-19 10:51:15 -05:00
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bootp	ARM: 8153/1: Enable gcov support on the ARM architecture	2014-09-26 14:39:57 +01:00
compressed	Merge branches 'debug', 'fixes', 'l2c' (early part), 'misc' and 'sa1100' into for-next	2015-02-10 10:26:27 +00:00
dts	ARM: socfpga: dts: fix spi1 interrupt	2015-03-19 10:51:15 -05:00
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