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72add915fb
Enable SGX virtualization now that KVM has the VM-Exit handlers needed to trap-and-execute ENCLS to ensure correctness and/or enforce the CPU model exposed to the guest. Add a KVM module param, "sgx", to allow an admin to disable SGX virtualization independent of the kernel. When supported in hardware and the kernel, advertise SGX1, SGX2 and SGX LC to userspace via CPUID and wire up the ENCLS_EXITING bitmap based on the guest's SGX capabilities, i.e. to allow ENCLS to be executed in an SGX-enabled guest. With the exception of the provision key, all SGX attribute bits may be exposed to the guest. Guest access to the provision key, which is controlled via securityfs, will be added in a future patch. Note, KVM does not yet support exposing ENCLS_C leafs or ENCLV leafs. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Kai Huang <kai.huang@intel.com> Message-Id: <a99e9c23310c79f2f4175c1af4c4cbcef913c3e5.1618196135.git.kai.huang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
298 lines
8.9 KiB
C
298 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_NESTED_H
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#define __KVM_X86_VMX_NESTED_H
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#include "kvm_cache_regs.h"
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#include "vmcs12.h"
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#include "vmx.h"
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/*
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* Status returned by nested_vmx_enter_non_root_mode():
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*/
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enum nvmx_vmentry_status {
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NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */
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NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */
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NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */
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NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */
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};
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void vmx_leave_nested(struct kvm_vcpu *vcpu);
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void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps);
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void nested_vmx_hardware_unsetup(void);
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__init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *));
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void nested_vmx_set_vmcs_shadowing_bitmap(void);
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void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu);
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enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
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bool from_vmentry);
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bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu);
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void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
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u32 exit_intr_info, unsigned long exit_qualification);
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void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu);
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int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
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int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata);
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int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
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u32 vmx_instruction_info, bool wr, int len, gva_t *ret);
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void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu);
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void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu);
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bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port,
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int size);
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static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
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{
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return to_vmx(vcpu)->nested.cached_vmcs12;
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}
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static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
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{
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return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
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}
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/*
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* Note: the same condition is checked against the state provided by userspace
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* in vmx_set_nested_state; if it is satisfied, the nested state must include
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* the VMCS12.
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*/
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static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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/*
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* In case we do two consecutive get/set_nested_state()s while L2 was
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* running hv_evmcs may end up not being mapped (we map it from
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* nested_vmx_run()/vmx_vcpu_run()). Check is_guest_mode() as we always
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* have vmcs12 if it is true.
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*/
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return is_guest_mode(vcpu) || vmx->nested.current_vmptr != -1ull ||
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vmx->nested.hv_evmcs;
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}
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static inline u16 nested_get_vpid02(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid;
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}
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static inline unsigned long nested_ept_get_eptp(struct kvm_vcpu *vcpu)
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{
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/* return the page table to be shadowed - in our case, EPT12 */
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return get_vmcs12(vcpu)->ept_pointer;
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}
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static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
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{
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return nested_ept_get_eptp(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
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}
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/*
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* Return the cr0 value that a nested guest would read. This is a combination
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* of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
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* its hypervisor (cr0_read_shadow).
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*/
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static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
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{
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return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
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(fields->cr0_read_shadow & fields->cr0_guest_host_mask);
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}
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static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
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{
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return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
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(fields->cr4_read_shadow & fields->cr4_guest_host_mask);
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}
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static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
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{
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return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
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}
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/*
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* Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
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* to modify any valid field of the VMCS, or are the VM-exit
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* information fields read-only?
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*/
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static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
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{
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return to_vmx(vcpu)->nested.msrs.misc_low &
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MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
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}
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static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
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{
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return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
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}
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static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
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{
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return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
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CPU_BASED_MONITOR_TRAP_FLAG;
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}
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static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
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{
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return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
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SECONDARY_EXEC_SHADOW_VMCS;
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}
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static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
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{
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return vmcs12->cpu_based_vm_exec_control & bit;
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}
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static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
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{
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return (vmcs12->cpu_based_vm_exec_control &
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
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(vmcs12->secondary_vm_exec_control & bit);
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}
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static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
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{
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return vmcs12->pin_based_vm_exec_control &
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PIN_BASED_VMX_PREEMPTION_TIMER;
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}
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static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
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{
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return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
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}
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static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
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{
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return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
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}
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static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
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}
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static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
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}
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static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
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}
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static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
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}
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static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
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}
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static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
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}
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static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
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}
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static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
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}
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static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
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{
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return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
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}
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static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
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}
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static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has_vmfunc(vmcs12) &&
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(vmcs12->vm_function_control &
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VMX_VMFUNC_EPTP_SWITCHING);
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}
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static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
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}
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static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12)
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{
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return vmcs12->vm_exit_controls &
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VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
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}
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static inline bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
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{
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return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
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}
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/*
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* In nested virtualization, check if L1 asked to exit on external interrupts.
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* For most existing hypervisors, this will always return true.
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*/
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static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
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{
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return get_vmcs12(vcpu)->pin_based_vm_exec_control &
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PIN_BASED_EXT_INTR_MASK;
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}
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static inline bool nested_cpu_has_encls_exit(struct vmcs12 *vmcs12)
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{
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING);
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}
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/*
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* if fixed0[i] == 1: val[i] must be 1
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* if fixed1[i] == 0: val[i] must be 0
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*/
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static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
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{
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return ((val & fixed1) | fixed0) == val;
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}
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static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
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{
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u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
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u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
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struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
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if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
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SECONDARY_EXEC_UNRESTRICTED_GUEST &&
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nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
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fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
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return fixed_bits_valid(val, fixed0, fixed1);
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}
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static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
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{
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u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
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u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
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return fixed_bits_valid(val, fixed0, fixed1);
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}
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static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
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{
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u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
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u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
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return fixed_bits_valid(val, fixed0, fixed1);
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}
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/* No difference in the restrictions on guest and host CR4 in VMX operation. */
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#define nested_guest_cr4_valid nested_cr4_valid
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#define nested_host_cr4_valid nested_cr4_valid
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extern struct kvm_x86_nested_ops vmx_nested_ops;
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#endif /* __KVM_X86_VMX_NESTED_H */
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