mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-26 20:44:32 +08:00
c913fc4146
These updates have been kept in a separate branch mostly because
they rely on updates to the respective clk drivers to keep the
shared header files in sync.
- The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
automotive SoC similar to the ⅹ8a7795 chip we already support, but
the dts changes rely on a clock driver change that has been
merged for v4.9 through the clk tree.
- The Amlogic meson-gxbb (S905) platform gains support for a few
drivers merged through our tree, in particular the network and
usb driver changes are required and included here, and also
the clk tree changes.
- The Allwinner platforms have seen a large-scale change to their
clk drivers and the dts file updates must come after that.
This includes the newly added Nextthing GR8 platform, which is
derived from sun5i/A13.
- Some integrator (arm32) changes rely on clk driver changes.
- A single patch for lpc32xx has no such dependency but wasn't
added until just before the merge window
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAV/gzeGCrR//JCVInAQKVhw/5AS5R2S7m7VTlWMvGjvH9ITudYhiAGJP1
z5nP5SwJsfmSjfvw0kSxGUmsNS3rHutsPMz65EesKqFuC3LPZiqMUqrzxt9iqqJx
I+XdAxDTnOE1RBZFtB9dL+qLzHQ87pMo6R9dfs32sxb3QuCQBYhcFyLmQDuZuHH0
yeDi3ARFvgxx/qoRUA7cnSlY5RLNzM44y+Ik/ZcVr4ReqYBC2g5mGi5htoiNSLWR
nwWR+5hNLAp44OZgkZfNsf6kB9brWDQh3PbnBjy6sKXSBoSVIfxTweh2DMJXbZ7l
1Ck+S7WyLMhGJp448TcuBykr/l9i3uqNh061XavjwP8CAjAdZ787XlnNSztc2pyh
dvbI/E76pLGb5ZoFdqlY2Syl63ZFN4K8mjZMSPYfYKf85EDIxe4MYwpbo7/pwzh3
8OlBwH6r4aUMw+QgE1nx8nsjaCoGDMFdgJeJJaWdriZ6Nst2n5gREk/mzbrAWkNG
ujChn/6hES9LuE21aCp1ipB7qnnyeRinfqz2acEFxMQxuPdjwKrdJqNsBaTWsapE
Z+b/BFP+LTdPfHCmMSVwfMrNbwsoY7+L4EXXL36lUgOwcDp0vCXA+PiiahYASewA
1LDQ3CURCEapdBhVU+06Kb4y5eWU7M7EqpOwpHgRJ92dVxgNxuCfcurvxzqPP1UP
3O4R7bfUTTg=
=OmAu
-----END PGP SIGNATURE-----
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late DT updates from Arnd Bergmann:
"These updates have been kept in a separate branch mostly because they
rely on updates to the respective clk drivers to keep the shared
header files in sync.
- The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
automotive SoC similar to the ⅹ8a7795 chip we already support, but
the dts changes rely on a clock driver change that has been merged
for v4.9 through the clk tree.
- The Amlogic meson-gxbb (S905) platform gains support for a few
drivers merged through our tree, in particular the network and usb
driver changes are required and included here, and also the clk
tree changes.
- The Allwinner platforms have seen a large-scale change to their clk
drivers and the dts file updates must come after that. This
includes the newly added Nextthing GR8 platform, which is derived
from sun5i/A13.
- Some integrator (arm32) changes rely on clk driver changes.
- A single patch for lpc32xx has no such dependency but wasn't added
until just before the merge window"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
ARM: dts: lpc32xx: add device node for IRAM on-chip memory
ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03
ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
ARM: dts: sun8i: add pinmux for UART1 at PG
dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
dts: sun8i-h3: add pinmux definitions for I2C0-2
dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
dts: sun8i-h3: add pinmux definitions for UART2-3
ARM: dts: sun9i: a80-optimus: Disable EHCI1
ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators
ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators
ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused
ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused
ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h
ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04
ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03
ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz
ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h
ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
...
927 lines
24 KiB
Plaintext
927 lines
24 KiB
Plaintext
/*
|
|
* Copyright 2013 Maxime Ripard
|
|
*
|
|
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/thermal/thermal.h>
|
|
|
|
#include <dt-bindings/clock/sun6i-a31-ccu.h>
|
|
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
|
#include <dt-bindings/reset/sun6i-a31-ccu.h>
|
|
|
|
/ {
|
|
interrupt-parent = <&gic>;
|
|
|
|
aliases {
|
|
ethernet0 = &gmac;
|
|
};
|
|
|
|
chosen {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
simplefb_hdmi: framebuffer@0 {
|
|
compatible = "allwinner,simple-framebuffer",
|
|
"simple-framebuffer";
|
|
allwinner,pipeline = "de_be0-lcd0-hdmi";
|
|
clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
|
|
<&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
|
|
<&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
|
|
<&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
|
|
status = "disabled";
|
|
};
|
|
|
|
simplefb_lcd: framebuffer@1 {
|
|
compatible = "allwinner,simple-framebuffer",
|
|
"simple-framebuffer";
|
|
allwinner,pipeline = "de_be0-lcd0";
|
|
clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
|
|
<&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
|
|
<&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <24000000>;
|
|
arm,cpu-registers-not-fw-configured;
|
|
};
|
|
|
|
cpus {
|
|
enable-method = "allwinner,sun6i-a31";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
clocks = <&ccu CLK_CPU>;
|
|
clock-latency = <244144>; /* 8 32k periods */
|
|
operating-points = <
|
|
/* kHz uV */
|
|
1008000 1200000
|
|
864000 1200000
|
|
720000 1100000
|
|
480000 1000000
|
|
>;
|
|
#cooling-cells = <2>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <3>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu_thermal {
|
|
/* milliseconds */
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&rtp>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_alert0>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
cpu_alert0: cpu_alert0 {
|
|
/* milliCelsius */
|
|
temperature = <70000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu_crit: cpu_crit {
|
|
/* milliCelsius */
|
|
temperature = <100000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
memory {
|
|
reg = <0x40000000 0x80000000>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
osc24M: osc24M {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
};
|
|
|
|
osc32k: clk@0 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "osc32k";
|
|
};
|
|
|
|
/*
|
|
* The following two are dummy clocks, placeholders
|
|
* used in the gmac_tx clock. The gmac driver will
|
|
* choose one parent depending on the PHY interface
|
|
* mode, using clk_set_rate auto-reparenting.
|
|
*
|
|
* The actual TX clock rate is not controlled by the
|
|
* gmac_tx clock.
|
|
*/
|
|
mii_phy_tx_clk: clk@1 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <25000000>;
|
|
clock-output-names = "mii_phy_tx";
|
|
};
|
|
|
|
gmac_int_tx_clk: clk@2 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <125000000>;
|
|
clock-output-names = "gmac_int_tx";
|
|
};
|
|
|
|
gmac_tx_clk: clk@01c200d0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun7i-a20-gmac-clk";
|
|
reg = <0x01c200d0 0x4>;
|
|
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
|
clock-output-names = "gmac_tx";
|
|
};
|
|
};
|
|
|
|
soc@01c00000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dma: dma-controller@01c02000 {
|
|
compatible = "allwinner,sun6i-a31-dma";
|
|
reg = <0x01c02000 0x1000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_DMA>;
|
|
resets = <&ccu RST_AHB1_DMA>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
mmc0: mmc@01c0f000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c0f000 0x1000>;
|
|
clocks = <&ccu CLK_AHB1_MMC0>,
|
|
<&ccu CLK_MMC0>,
|
|
<&ccu CLK_MMC0_OUTPUT>,
|
|
<&ccu CLK_MMC0_SAMPLE>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ccu RST_AHB1_MMC0>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc1: mmc@01c10000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c10000 0x1000>;
|
|
clocks = <&ccu CLK_AHB1_MMC1>,
|
|
<&ccu CLK_MMC1>,
|
|
<&ccu CLK_MMC1_OUTPUT>,
|
|
<&ccu CLK_MMC1_SAMPLE>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ccu RST_AHB1_MMC1>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@01c11000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c11000 0x1000>;
|
|
clocks = <&ccu CLK_AHB1_MMC2>,
|
|
<&ccu CLK_MMC2>,
|
|
<&ccu CLK_MMC2_OUTPUT>,
|
|
<&ccu CLK_MMC2_SAMPLE>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ccu RST_AHB1_MMC2>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc3: mmc@01c12000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c12000 0x1000>;
|
|
clocks = <&ccu CLK_AHB1_MMC3>,
|
|
<&ccu CLK_MMC3>,
|
|
<&ccu CLK_MMC3_OUTPUT>,
|
|
<&ccu CLK_MMC3_SAMPLE>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ccu RST_AHB1_MMC3>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
usb_otg: usb@01c19000 {
|
|
compatible = "allwinner,sun6i-a31-musb";
|
|
reg = <0x01c19000 0x0400>;
|
|
clocks = <&ccu CLK_AHB1_OTG>;
|
|
resets = <&ccu RST_AHB1_OTG>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
extcon = <&usbphy 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@01c19400 {
|
|
compatible = "allwinner,sun6i-a31-usb-phy";
|
|
reg = <0x01c19400 0x10>,
|
|
<0x01c1a800 0x4>,
|
|
<0x01c1b800 0x4>;
|
|
reg-names = "phy_ctrl",
|
|
"pmu1",
|
|
"pmu2";
|
|
clocks = <&ccu CLK_USB_PHY0>,
|
|
<&ccu CLK_USB_PHY1>,
|
|
<&ccu CLK_USB_PHY2>;
|
|
clock-names = "usb0_phy",
|
|
"usb1_phy",
|
|
"usb2_phy";
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
<&ccu RST_USB_PHY1>,
|
|
<&ccu RST_USB_PHY2>;
|
|
reset-names = "usb0_reset",
|
|
"usb1_reset",
|
|
"usb2_reset";
|
|
status = "disabled";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
ehci0: usb@01c1a000 {
|
|
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
|
|
reg = <0x01c1a000 0x100>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_EHCI0>;
|
|
resets = <&ccu RST_AHB1_EHCI0>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@01c1a400 {
|
|
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
|
|
reg = <0x01c1a400 0x100>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_AHB1_OHCI0>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@01c1b000 {
|
|
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
|
|
reg = <0x01c1b000 0x100>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_EHCI1>;
|
|
resets = <&ccu RST_AHB1_EHCI1>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@01c1b400 {
|
|
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
|
|
reg = <0x01c1b400 0x100>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
|
|
resets = <&ccu RST_AHB1_OHCI1>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci2: usb@01c1c400 {
|
|
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
|
|
reg = <0x01c1c400 0x100>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
|
|
resets = <&ccu RST_AHB1_OHCI2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ccu: clock@01c20000 {
|
|
compatible = "allwinner,sun6i-a31-ccu";
|
|
reg = <0x01c20000 0x400>;
|
|
clocks = <&osc24M>, <&osc32k>;
|
|
clock-names = "hosc", "losc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pio: pinctrl@01c20800 {
|
|
compatible = "allwinner,sun6i-a31-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_PIO>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
allwinner,pins = "PH20", "PH21";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
allwinner,pins = "PH14", "PH15";
|
|
allwinner,function = "i2c0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
allwinner,pins = "PH16", "PH17";
|
|
allwinner,function = "i2c1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
allwinner,pins = "PH18", "PH19";
|
|
allwinner,function = "i2c2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
allwinner,pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
allwinner,function = "mmc0";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc1_pins_a: mmc1@0 {
|
|
allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
|
"PG4", "PG5";
|
|
allwinner,function = "mmc1";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc2_pins_a: mmc2@0 {
|
|
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
mmc2_8bit_emmc_pins: mmc2@1 {
|
|
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12",
|
|
"PC13", "PC14", "PC15",
|
|
"PC24";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc3_8bit_emmc_pins: mmc3@1 {
|
|
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12",
|
|
"PC13", "PC14", "PC15",
|
|
"PC24";
|
|
allwinner,function = "mmc3";
|
|
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_mii_a: gmac_mii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
|
"PA8", "PA9", "PA11",
|
|
"PA12", "PA13", "PA14", "PA19",
|
|
"PA20", "PA21", "PA22", "PA23",
|
|
"PA24", "PA26", "PA27";
|
|
allwinner,function = "gmac";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_gmii_a: gmac_gmii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
|
"PA4", "PA5", "PA6", "PA7",
|
|
"PA8", "PA9", "PA10", "PA11",
|
|
"PA12", "PA13", "PA14", "PA15",
|
|
"PA16", "PA17", "PA18", "PA19",
|
|
"PA20", "PA21", "PA22", "PA23",
|
|
"PA24", "PA25", "PA26", "PA27";
|
|
allwinner,function = "gmac";
|
|
/*
|
|
* data lines in GMII mode run at 125MHz and
|
|
* might need a higher signal drive strength
|
|
*/
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
|
"PA9", "PA10", "PA11",
|
|
"PA12", "PA13", "PA14", "PA19",
|
|
"PA20", "PA25", "PA26", "PA27";
|
|
allwinner,function = "gmac";
|
|
/*
|
|
* data lines in RGMII mode use DDR mode
|
|
* and need a higher signal drive strength
|
|
*/
|
|
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0xa0>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt1: watchdog@01c20ca0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x01c20ca0 0x20>;
|
|
};
|
|
|
|
lradc: lradc@01c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtp: rtp@01c25000 {
|
|
compatible = "allwinner,sun6i-a31-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB2_UART0>;
|
|
resets = <&ccu RST_APB2_UART0>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB2_UART1>;
|
|
resets = <&ccu RST_APB2_UART1>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB2_UART2>;
|
|
resets = <&ccu RST_APB2_UART2>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB2_UART3>;
|
|
resets = <&ccu RST_APB2_UART3>;
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB2_UART4>;
|
|
resets = <&ccu RST_APB2_UART4>;
|
|
dmas = <&dma 10>, <&dma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@01c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB2_UART5>;
|
|
resets = <&ccu RST_APB2_UART5>;
|
|
dmas = <&dma 22>, <&dma 22>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB2_I2C0>;
|
|
resets = <&ccu RST_APB2_I2C0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB2_I2C1>;
|
|
resets = <&ccu RST_APB2_I2C1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB2_I2C2>;
|
|
resets = <&ccu RST_APB2_I2C2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@01c2b800 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b800 0x400>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB2_I2C3>;
|
|
resets = <&ccu RST_APB2_I2C3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gmac: ethernet@01c30000 {
|
|
compatible = "allwinner,sun7i-a20-gmac";
|
|
reg = <0x01c30000 0x1054>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
|
|
clock-names = "stmmaceth", "allwinner_gmac_tx";
|
|
resets = <&ccu RST_AHB1_EMAC>;
|
|
reset-names = "stmmaceth";
|
|
snps,pbl = <2>;
|
|
snps,fixed-burst;
|
|
snps,force_sf_dma_mode;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
crypto: crypto-engine@01c15000 {
|
|
compatible = "allwinner,sun4i-a10-crypto";
|
|
reg = <0x01c15000 0x1000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ccu RST_AHB1_SS>;
|
|
reset-names = "ahb";
|
|
};
|
|
|
|
timer@01c60000 {
|
|
compatible = "allwinner,sun6i-a31-hstimer",
|
|
"allwinner,sun7i-a20-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_HSTIMER>;
|
|
resets = <&ccu RST_AHB1_HSTIMER>;
|
|
};
|
|
|
|
spi0: spi@01c68000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c68000 0x1000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 23>, <&dma 23>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_AHB1_SPI0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@01c69000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c69000 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 24>, <&dma 24>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_AHB1_SPI1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@01c6a000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c6a000 0x1000>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 25>, <&dma 25>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_AHB1_SPI2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@01c6b000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c6b000 0x1000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 26>, <&dma 26>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_AHB1_SPI3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
rtc: rtc@01f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
nmi_intc: interrupt-controller@01f00c0c {
|
|
compatible = "allwinner,sun6i-a31-sc-nmi";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x01f00c0c 0x38>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
prcm@01f01400 {
|
|
compatible = "allwinner,sun6i-a31-prcm";
|
|
reg = <0x01f01400 0x200>;
|
|
|
|
ar100: ar100_clk {
|
|
compatible = "allwinner,sun6i-a31-ar100-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&osc32k>, <&osc24M>,
|
|
<&ccu CLK_PLL_PERIPH>,
|
|
<&ccu CLK_PLL_PERIPH>;
|
|
clock-output-names = "ar100";
|
|
};
|
|
|
|
ahb0: ahb0_clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&ar100>;
|
|
clock-output-names = "ahb0";
|
|
};
|
|
|
|
apb0: apb0_clk {
|
|
compatible = "allwinner,sun6i-a31-apb0-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&ahb0>;
|
|
clock-output-names = "apb0";
|
|
};
|
|
|
|
apb0_gates: apb0_gates_clk {
|
|
compatible = "allwinner,sun6i-a31-apb0-gates-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&apb0>;
|
|
clock-output-names = "apb0_pio", "apb0_ir",
|
|
"apb0_timer", "apb0_p2wi",
|
|
"apb0_uart", "apb0_1wire",
|
|
"apb0_i2c";
|
|
};
|
|
|
|
ir_clk: ir_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
clocks = <&osc32k>, <&osc24M>;
|
|
clock-output-names = "ir";
|
|
};
|
|
|
|
apb0_rst: apb0_rst {
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
cpucfg@01f01c00 {
|
|
compatible = "allwinner,sun6i-a31-cpuconfig";
|
|
reg = <0x01f01c00 0x300>;
|
|
};
|
|
|
|
ir: ir@01f02000 {
|
|
compatible = "allwinner,sun5i-a13-ir";
|
|
clocks = <&apb0_gates 1>, <&ir_clk>;
|
|
clock-names = "apb", "ir";
|
|
resets = <&apb0_rst 1>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01f02000 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_pio: pinctrl@01f02c00 {
|
|
compatible = "allwinner,sun6i-a31-r-pinctrl";
|
|
reg = <0x01f02c00 0x400>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 0>;
|
|
resets = <&apb0_rst 0>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <3>;
|
|
|
|
ir_pins_a: ir@0 {
|
|
allwinner,pins = "PL4";
|
|
allwinner,function = "s_ir";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
p2wi_pins: p2wi {
|
|
allwinner,pins = "PL0", "PL1";
|
|
allwinner,function = "s_p2wi";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
p2wi: i2c@01f03400 {
|
|
compatible = "allwinner,sun6i-a31-p2wi";
|
|
reg = <0x01f03400 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 3>;
|
|
clock-frequency = <100000>;
|
|
resets = <&apb0_rst 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&p2wi_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|