Vincent Chen 1a0e5dbd37 riscv: sifive: Add SiFive alternative ports ... Add required ports of the Alternative scheme for SiFive. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-04-26 08:24:56 -07:00
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asm	riscv: sifive: Add SiFive alternative ports	2021-04-26 08:24:56 -07:00
uapi/asm	riscv: Add cache information in AUX vector	2020-09-15 18:46:08 -07:00