mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 15:04:27 +08:00
62b0194368
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
34 lines
990 B
C
34 lines
990 B
C
/*
|
|
* Copyright (C) 2012 Regents of the University of California
|
|
* Copyright (C) 2017 SiFive
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation, version 2.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <linux/clocksource.h>
|
|
#include <linux/delay.h>
|
|
#include <asm/sbi.h>
|
|
|
|
unsigned long riscv_timebase;
|
|
|
|
void __init time_init(void)
|
|
{
|
|
struct device_node *cpu;
|
|
u32 prop;
|
|
|
|
cpu = of_find_node_by_path("/cpus");
|
|
if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
|
|
panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
|
|
riscv_timebase = prop;
|
|
|
|
lpj_fine = riscv_timebase / HZ;
|
|
timer_probe();
|
|
}
|