linux/drivers/cxl
Alison Schofield 18f35dc931 cxl/region: Refactor granularity select in cxl_port_setup_targets()
In cxl_port_setup_targets() the region driver validates the
configuration of auto-discovered region decoders, as well
as decoders the driver is preparing to program.

The existing calculations use the encoded interleave granularity
value to create an interleave granularity that properly fans out
when routing an x1 interleave to a greater than x1 interleave.

That all worked well, until this config came along:
Host Bridge: 2 way at 256 granularity
    Switch Decoder_A:	1 way at 512
        Endpoint_X:	2 way at 256
    Switch Decoder_B:	1 way at 512
        Endpoint_Y:	2 way at 256

When the Host Bridge interleave is greater than 1 and the root
decoder interleave is exactly 1, the region driver needs to
consider the number of targets in the region when calculating
the expected granularity.

While examining the existing logic, and trying to cover the case
above, a couple of simplifications appeared, hence this proposed
refactoring.

The first simplification is to apply the logic to the nominal
values and use the existing helper function granularity_to_eig() to
translate the desired granularity to the encoded form. This means
the comment and code regarding setting address bits is discarded.
Although that logic is not wrong, it adds a level of complexity that
is not required in the granularity selection. The eig and eiw are
indeed part of the routing instructions programmed into the decoders.
Up-level the discussion to nominal ways and granularity for clearer
analysis.

The second simplification reduces the logic to a single granularity
calculation that works for all cases. The new calculation doesn't
care if parent_iw => 1 because parent_iw is used as a multiplier.

The refactor cleans up a useless assignment of eiw made after the
iw is already calculated.

Regression testing included an examination of all of the ways and
granularity selections made during a run of the cxl_test unit tests.
There were no differences in selections before and after this patch.

Fixes: ("27b3f8d13830 cxl/region: Program target lists")
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20230822180928.117596-1-alison.schofield@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-09-14 20:47:42 -07:00
..
core cxl/region: Refactor granularity select in cxl_port_setup_targets() 2023-09-14 20:47:42 -07:00
acpi.c cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws() 2023-07-18 11:55:09 -06:00
cxl.h Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
cxlmem.h cxl/memdev: Only show sanitize sysfs files when supported 2023-07-28 13:16:54 -06:00
cxlpci.h cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
Kconfig cxl: fix CONFIG_FW_LOADER dependency 2023-07-14 14:32:22 -06:00
Makefile cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation 2022-11-30 16:30:47 -08:00
mem.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
pci.c cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() 2023-09-11 15:24:30 -07:00
pmem.c cxl/mbox: Move mailbox related driver state to its own data structure 2023-06-25 14:31:08 -07:00
pmu.h cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
port.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
security.c Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl 2023-06-25 17:16:51 -07:00