mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-28 13:34:38 +08:00
e042f151ec
Fix Documentation/hwmon/ kernel-doc warning in 5.11-rc1:
lnx-511-rc1/Documentation/hwmon/sbtsi_temp.rst:4: WARNING: Title underline too short.
Kernel driver sbtsi_temp
==================
Fixes: 6ec3fcf556
("hwmon: (sbtsi) Add documentation")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Kun Yi <kunyi@google.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Jean Delvare <jdelvare@suse.com>
Cc: linux-hwmon@vger.kernel.org
Link: https://lore.kernel.org/r/20201229035428.31270-1-rdunlap@infradead.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
43 lines
1.5 KiB
ReStructuredText
43 lines
1.5 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
Kernel driver sbtsi_temp
|
|
========================
|
|
|
|
Supported hardware:
|
|
|
|
* Sideband interface (SBI) Temperature Sensor Interface (SB-TSI)
|
|
compliant AMD SoC temperature device.
|
|
|
|
Prefix: 'sbtsi_temp'
|
|
|
|
Addresses scanned: This driver doesn't support address scanning.
|
|
|
|
To instantiate this driver on an AMD CPU with SB-TSI
|
|
support, the i2c bus number would be the bus connected from the board
|
|
management controller (BMC) to the CPU. The i2c address is specified in
|
|
Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
|
|
98h for socket 0 and 90h for socket 1, but it could vary based on hardware
|
|
address select pins.
|
|
|
|
Datasheet: The SB-TSI interface and protocol is available as part of
|
|
the open source SoC register reference at:
|
|
|
|
https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf
|
|
|
|
The Advanced Platform Management Link (APML) Specification is
|
|
available at:
|
|
|
|
http://developer.amd.com/wordpress/media/2012/10/41918.pdf
|
|
|
|
Author: Kun Yi <kunyi@google.com>
|
|
|
|
Description
|
|
-----------
|
|
|
|
The SBI temperature sensor interface (SB-TSI) is an emulation of the software
|
|
and physical interface of a typical 8-pin remote temperature sensor (RTS) on
|
|
AMD SoCs. It implements one temperature sensor with readings and limit
|
|
registers encode the temperature in increments of 0.125 from 0 to 255.875.
|
|
Limits can be set through the writable thresholds, and if reached will trigger
|
|
corresponding alert signals.
|