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Now that sdhci_pltfm_unregister() has been removed, rename sdhci_pltfm_register() to sdhci_pltfm_init_and_add_host() to better reflect what it does. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230811130351.7038-17-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
124 lines
3.2 KiB
C
124 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2010 MontaVista Software, LLC.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
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#define _DRIVERS_MMC_SDHCI_PLTFM_H
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include "sdhci.h"
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struct sdhci_pltfm_data {
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const struct sdhci_ops *ops;
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unsigned int quirks;
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unsigned int quirks2;
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};
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struct sdhci_pltfm_host {
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struct clk *clk;
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/* migrate from sdhci_of_host */
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unsigned int clock;
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u16 xfer_mode_shadow;
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unsigned long private[] ____cacheline_aligned;
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};
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#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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/*
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* These accessors are designed for big endian hosts doing I/O to
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* little endian controllers incorporating a 32-bit hardware byte swapper.
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*/
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static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
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{
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return in_be32(host->ioaddr + reg);
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}
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static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
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{
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return in_be16(host->ioaddr + (reg ^ 0x2));
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}
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static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
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{
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return in_8(host->ioaddr + (reg ^ 0x3));
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}
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static inline void sdhci_be32bs_writel(struct sdhci_host *host,
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u32 val, int reg)
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{
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out_be32(host->ioaddr + reg, val);
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}
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static inline void sdhci_be32bs_writew(struct sdhci_host *host,
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u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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pltfm_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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sdhci_be32bs_writel(host,
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val << 16 | pltfm_host->xfer_mode_shadow,
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SDHCI_TRANSFER_MODE);
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return;
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}
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clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
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}
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static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
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}
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#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
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void sdhci_get_property(struct platform_device *pdev);
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static inline void sdhci_get_of_property(struct platform_device *pdev)
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{
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return sdhci_get_property(pdev);
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}
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extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
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const struct sdhci_pltfm_data *pdata,
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size_t priv_size);
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extern void sdhci_pltfm_free(struct platform_device *pdev);
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extern int sdhci_pltfm_init_and_add_host(struct platform_device *pdev,
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const struct sdhci_pltfm_data *pdata,
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size_t priv_size);
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extern void sdhci_pltfm_remove(struct platform_device *pdev);
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extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
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static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
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{
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return host->private;
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}
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extern const struct dev_pm_ops sdhci_pltfm_pmops;
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#ifdef CONFIG_PM_SLEEP
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int sdhci_pltfm_suspend(struct device *dev);
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int sdhci_pltfm_resume(struct device *dev);
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#else
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static inline int sdhci_pltfm_suspend(struct device *dev) { return 0; }
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static inline int sdhci_pltfm_resume(struct device *dev) { return 0; }
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#endif
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#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */
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