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6c0afb5039
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
291 lines
6.7 KiB
C
291 lines
6.7 KiB
C
/*
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* TI Multiplexer Clock
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_omap_mux *mux = to_clk_omap_mux(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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u32 val;
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/*
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* FIXME need a mux-specific flag to determine if val is bitwise or
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* numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
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* from 0x1 to 0x7 (index starts at one)
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* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
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* val = 0x4 really means "bit 2, index starts at bit 0"
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*/
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val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
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val &= mux->mask;
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if (mux->table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (mux->table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (mux->flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (mux->flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_omap_mux *mux = to_clk_omap_mux(hw);
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u32 val;
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if (mux->table) {
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index = mux->table[index];
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} else {
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if (mux->flags & CLK_MUX_INDEX_BIT)
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index = (1 << ffs(index));
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if (mux->flags & CLK_MUX_INDEX_ONE)
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index++;
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}
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
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val = mux->mask << (mux->shift + 16);
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} else {
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val = ti_clk_ll_ops->clk_readl(&mux->reg);
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val &= ~(mux->mask << mux->shift);
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}
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val |= index << mux->shift;
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ti_clk_ll_ops->clk_writel(val, &mux->reg);
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return 0;
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}
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const struct clk_ops ti_clk_mux_ops = {
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.get_parent = ti_clk_mux_get_parent,
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.set_parent = ti_clk_mux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static struct clk *_register_mux(struct device *dev, const char *name,
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const char * const *parent_names,
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u8 num_parents, unsigned long flags,
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struct clk_omap_reg *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table)
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{
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struct clk_omap_mux *mux;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the mux */
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux) {
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pr_err("%s: could not allocate mux clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &ti_clk_mux_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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/* struct clk_mux assignments */
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memcpy(&mux->reg, reg, sizeof(*reg));
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->table = table;
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mux->hw.init = &init;
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clk = ti_clk_register(dev, &mux->hw, name);
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if (IS_ERR(clk))
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kfree(mux);
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return clk;
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}
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struct clk *ti_clk_register_mux(struct ti_clk *setup)
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{
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struct ti_clk_mux *mux;
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u32 flags;
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u8 mux_flags = 0;
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struct clk_omap_reg reg;
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u32 mask;
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mux = setup->data;
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flags = CLK_SET_RATE_NO_REPARENT;
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mask = mux->num_parents;
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if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
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mask--;
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mask = (1 << fls(mask)) - 1;
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reg.index = mux->module;
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reg.offset = mux->reg;
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reg.ptr = NULL;
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if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
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mux_flags |= CLK_MUX_INDEX_ONE;
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if (mux->flags & CLKF_SET_RATE_PARENT)
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flags |= CLK_SET_RATE_PARENT;
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return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
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flags, ®, mux->bit_shift, mask,
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mux_flags, NULL);
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}
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/**
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* of_mux_clk_setup - Setup function for simple mux rate clock
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* @node: DT node for the clock
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*
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* Sets up a basic clock multiplexer.
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*/
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static void of_mux_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_omap_reg reg;
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unsigned int num_parents;
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const char **parent_names;
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u8 clk_mux_flags = 0;
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u32 mask = 0;
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u32 shift = 0;
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u32 flags = CLK_SET_RATE_NO_REPARENT;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 2) {
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pr_err("mux-clock %s must have parents\n", node->name);
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return;
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}
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parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
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if (!parent_names)
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goto cleanup;
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of_clk_parent_fill(node, parent_names, num_parents);
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if (ti_clk_get_reg_addr(node, 0, ®))
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goto cleanup;
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of_property_read_u32(node, "ti,bit-shift", &shift);
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if (of_property_read_bool(node, "ti,index-starts-at-one"))
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clk_mux_flags |= CLK_MUX_INDEX_ONE;
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if (of_property_read_bool(node, "ti,set-rate-parent"))
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flags |= CLK_SET_RATE_PARENT;
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/* Generate bit-mask based on parent info */
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mask = num_parents;
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if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
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mask--;
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mask = (1 << fls(mask)) - 1;
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clk = _register_mux(NULL, node->name, parent_names, num_parents,
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flags, ®, shift, mask, clk_mux_flags, NULL);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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cleanup:
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kfree(parent_names);
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}
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CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
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struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
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{
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struct clk_omap_mux *mux;
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int num_parents;
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if (!setup)
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return NULL;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->shift = setup->bit_shift;
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mux->reg.index = setup->module;
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mux->reg.offset = setup->reg;
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if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
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mux->flags |= CLK_MUX_INDEX_ONE;
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num_parents = setup->num_parents;
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mux->mask = num_parents - 1;
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mux->mask = (1 << fls(mux->mask)) - 1;
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return &mux->hw;
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}
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static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
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{
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struct clk_omap_mux *mux;
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unsigned int num_parents;
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u32 val;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return;
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if (ti_clk_get_reg_addr(node, 0, &mux->reg))
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goto cleanup;
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if (!of_property_read_u32(node, "ti,bit-shift", &val))
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mux->shift = val;
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if (of_property_read_bool(node, "ti,index-starts-at-one"))
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mux->flags |= CLK_MUX_INDEX_ONE;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 2) {
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pr_err("%s must have parents\n", node->name);
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goto cleanup;
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}
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mux->mask = num_parents - 1;
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mux->mask = (1 << fls(mux->mask)) - 1;
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if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
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return;
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cleanup:
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kfree(mux);
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}
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CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
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of_ti_composite_mux_clk_setup);
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