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07f08d9cee
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
143 lines
2.9 KiB
Plaintext
143 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Speedy Rev 1+ board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "cros-ec-sbs.dtsi"
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/ {
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model = "Google Speedy";
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compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
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"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
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"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
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"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
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"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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panel_regulator: panel-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_enable_h>;
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regulator-name = "panel_regulator";
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startup-delay-us = <100000>;
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vin-supply = <&vcc33_sys>;
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};
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vcc18_lcd: vcc18-lcd {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&avdd_1v8_disp_en>;
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regulator-name = "vcc18_lcd";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc18_wl>;
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};
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backlight_regulator: backlight-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl_pwr_en>;
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regulator-name = "backlight_regulator";
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vin-supply = <&vcc33_sys>;
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startup-delay-us = <15000>;
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};
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};
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&backlight {
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power-supply = <&backlight_regulator>;
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};
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&cpu_alert0 {
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temperature = <65000>;
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};
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&cpu_alert1 {
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temperature = <70000>;
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};
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&edp {
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/delete-property/pinctrl-names;
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/delete-property/pinctrl-0;
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force-hpd;
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};
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&panel {
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power-supply= <&panel_regulator>;
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l>;
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};
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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_bus4>;
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};
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&vcc_5v {
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enable-active-high;
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gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&drv_5v>;
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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&pinctrl {
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backlight {
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bl_pwr_en: bl_pwr_en {
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rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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buck-5v {
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drv_5v: drv-5v {
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rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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hdmi {
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vcc50_hdmi_en: vcc50-hdmi-en {
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rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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lcd {
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lcd_enable_h: lcd-en {
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rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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avdd_1v8_disp_en: avdd-1v8-disp-en {
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rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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