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c6e967ad5a
With wlcore supporting optional wakeirqs, let's configure it for omap3-evm and update the related pin muxing as some pins are left unmuxed. Let's configure a wakeirq both for the wlcore GPIO and the SDIO dat1 pin in case wlcore starts supporting SDIO dat1 interrupt at some point. Note that for off-mode, the wlcore reset GPIO will have a glitch meaning wlcore will reset. The only way to workaround for this currently is to configure the reset pin with SAFE_MODE + PULL. Signed-off-by: Tony Lindgren <tony@atomide.com>
225 lines
7.7 KiB
Plaintext
225 lines
7.7 KiB
Plaintext
/*
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* Common support for omap3 EVM 35xx/37xx processor modules
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*/
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/ {
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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wl12xx_vmmc: wl12xx_vmmc {
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pinctrl-names = "default";
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pinctrl-0 = <&wl12xx_gpio>;
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};
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};
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&dss {
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vdds_dsi-supply = <&vpll2>;
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vdda_video-supply = <&lcd_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <
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&dss_dpi_pins1
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&dss_dpi_pins2
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>;
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};
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&hsusb2_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&ehci_phy_pins>;
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};
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
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dss_dpi_pins1: pinmux_dss_dpi_pins2 {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
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OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
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OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
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OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
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OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
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OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
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OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
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OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
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OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
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OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
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OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
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OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
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OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
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OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
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OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
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OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
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OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
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OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
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OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
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OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
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OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
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OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
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OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
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OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
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OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
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OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
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OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
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OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
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OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
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OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
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OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
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>;
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};
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/* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
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mmc2_pins: pinmux_mmc2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
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OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
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OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
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OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
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OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
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OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
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OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
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OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
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OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
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OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
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OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
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>;
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};
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/* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */
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on_board_gpio_61: pinmux_ehci_port_select_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4)
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>;
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};
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/* Used by OHCI and EHCI. OHCI won't work without external phy */
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hsusb2_pins: pinmux_hsusb2_pins {
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pinctrl-single,pins = <
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/* mcspi1_cs3.hsusb2_data2 */
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OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* mcspi2_clk.hsusb2_data7 */
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OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* mcspi2_simo.hsusb2_data4 */
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OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* mcspi2_somi.hsusb2_data5 */
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OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* mcspi2_cs0.hsusb2_data6 */
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OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* mcspi2_cs1.hsusb2_data3 */
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OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)
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>;
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};
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/*
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* Note that gpio_150 pulled high with internal pull to prevent wlcore
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* reset on return from off mode in idle.
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*/
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wl12xx_gpio: pinmux_wl12xx_gpio {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */
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OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
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>;
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};
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smsc911x_pins: pinmux_smsc911x_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
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>;
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};
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};
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&omap3_pmx_wkup {
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dss_dpi_pins2: pinmux_dss_dpi_pins1 {
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pinctrl-single,pins = <
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OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
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OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
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OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
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OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
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OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
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OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
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>;
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};
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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};
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_pins>;
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};
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&mmc3 {
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status = "disabled";
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};
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&uart1 {
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interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
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};
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&uart2 {
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interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
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};
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&uart3 {
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interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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};
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/*
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* GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface
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* for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
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*/
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&gpio2 {
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en_usb2_port {
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gpio-hog;
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gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */
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output-low;
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line-name = "enable usb2 port";
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};
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};
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/* T2_GPIO_2 low to route GPIO_61 to on-board devices */
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&twl_gpio {
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en_on_board_gpio_61 {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "en_hsusb2_clk";
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};
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};
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&gpmc {
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ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
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<5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */
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ethernet@gpmc {
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pinctrl-names = "default";
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pinctrl-0 = <&smsc911x_pins>;
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};
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};
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