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16ee792e45
* 'next/devel' of git://git.linaro.org/people/arnd/arm-soc: (50 commits) ARM: tegra: update defconfig arm/tegra: Harmony: Configure PMC for low-level interrupts arm/tegra: device tree support for ventana board arm/tegra: add support for ventana pinmuxing arm/tegra: prepare Seaboard pinmux code for derived boards arm/tegra: pinmux: ioremap registers gpio/tegra: Convert to a platform device arm/tegra: Convert pinmux driver to a platform device arm/dt: Tegra: Add pinmux node to tegra20.dtsi arm/tegra: Prep boards for gpio/pinmux conversion to pdevs ARM: mx5: fix clock usage for suspend ARM i.MX entry-macro.S: remove now unused code ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLER ARM i.MX tzic: add handle_irq function ARM i.MX avic: add handle_irq function ARM: mx25: Add the missing IIM base definition ARM i.MX avic: convert to use generic irq chip mx31moboard: Add poweroff support ARM: mach-qong: Add watchdog support ARM: davinci: AM18x: Add wl1271/wlan support ... Fix up conflicts in: arch/arm/mach-at91/at91sam9g45.c arch/arm/mach-mx5/devices-imx53.h arch/arm/plat-mxc/include/mach/memory.h
291 lines
7.1 KiB
C
291 lines
7.1 KiB
C
/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/smsc911x.h>
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#include <linux/mfd/mc13783.h>
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#include <linux/spi/spi.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/ulpi.h>
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#include <linux/mtd/physmap.h>
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#include <linux/delay.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/board-mx31lite.h>
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#include <mach/iomux-mx3.h>
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#include <mach/irqs.h>
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#include <mach/ulpi.h>
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#include "devices-imx31.h"
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/*
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* This file contains the module-specific initialization routines.
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*/
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static unsigned int mx31lite_pins[] = {
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/* LAN9117 IRQ pin */
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IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
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/* SPI 1 */
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MX31_PIN_CSPI2_SCLK__SCLK,
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MX31_PIN_CSPI2_MOSI__MOSI,
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MX31_PIN_CSPI2_MISO__MISO,
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MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
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MX31_PIN_CSPI2_SS0__SS0,
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MX31_PIN_CSPI2_SS1__SS1,
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MX31_PIN_CSPI2_SS2__SS2,
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};
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static const struct mxc_nand_platform_data
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mx31lite_nand_board_info __initconst = {
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.width = 1,
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.hw_ecc = 1,
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};
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static struct smsc911x_platform_config smsc911x_config = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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.flags = SMSC911X_USE_16BIT,
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};
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static struct resource smsc911x_resources[] = {
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{
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.start = MX31_CS4_BASE_ADDR,
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.end = MX31_CS4_BASE_ADDR + 0x100,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
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.end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smsc911x_device = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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};
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/*
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* SPI
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*
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* The MC13783 is the only hard-wired SPI device on the module.
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*/
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static int spi_internal_chipselect[] = {
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MXC_SPI_CS(0),
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};
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static const struct spi_imx_master spi1_pdata __initconst = {
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.chipselect = spi_internal_chipselect,
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.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
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};
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static struct mc13xxx_platform_data mc13783_pdata __initdata = {
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.flags = MC13XXX_USE_RTC |
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MC13XXX_USE_REGULATOR,
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};
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static struct spi_board_info mc13783_spi_dev __initdata = {
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.modalias = "mc13783",
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.max_speed_hz = 1000000,
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.bus_num = 1,
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.chip_select = 0,
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.platform_data = &mc13783_pdata,
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.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
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};
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/*
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* USB
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*/
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#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
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PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
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static int usbh2_init(struct platform_device *pdev)
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{
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int pins[] = {
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MX31_PIN_USBH2_DATA0__USBH2_DATA0,
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MX31_PIN_USBH2_DATA1__USBH2_DATA1,
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MX31_PIN_USBH2_CLK__USBH2_CLK,
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MX31_PIN_USBH2_DIR__USBH2_DIR,
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MX31_PIN_USBH2_NXT__USBH2_NXT,
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MX31_PIN_USBH2_STP__USBH2_STP,
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};
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mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
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mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
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mxc_iomux_set_gpr(MUX_PGP_UH2, true);
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/* chip select */
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mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
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"USBH2_CS");
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gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
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gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
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mdelay(10);
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return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
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}
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static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
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.init = usbh2_init,
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.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
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};
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/*
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* NOR flash
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*/
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static struct physmap_flash_data nor_flash_data = {
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.width = 2,
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};
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static struct resource nor_flash_resource = {
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.start = 0xa0000000,
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.end = 0xa1ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device physmap_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &nor_flash_data,
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},
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.resource = &nor_flash_resource,
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.num_resources = 1,
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};
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/*
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* This structure defines the MX31 memory map.
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*/
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static struct map_desc mx31lite_io_desc[] __initdata = {
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{
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.virtual = MX31_CS4_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
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.length = MX31_CS4_SIZE,
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.type = MT_DEVICE
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}
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};
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/*
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* Set up static virtual mappings.
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*/
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void __init mx31lite_map_io(void)
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{
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mx31_map_io();
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iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
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}
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static int mx31lite_baseboard;
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core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
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static void __init mx31lite_init(void)
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{
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int ret;
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imx31_soc_init();
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switch (mx31lite_baseboard) {
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case MX31LITE_NOBOARD:
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break;
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case MX31LITE_DB:
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mx31lite_db_init();
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break;
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default:
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printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
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mx31lite_baseboard);
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}
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mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
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"mx31lite");
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/* NOR and NAND flash */
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platform_device_register(&physmap_flash_device);
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imx31_add_mxc_nand(&mx31lite_nand_board_info);
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imx31_add_spi_imx1(&spi1_pdata);
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spi_register_board_info(&mc13783_spi_dev, 1);
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/* USB */
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usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
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ULPI_OTG_DRVVBUS_EXT);
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if (usbh2_pdata.otg)
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imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
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/* SMSC9117 IRQ pin */
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ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
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if (ret)
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pr_warning("could not get LAN irq gpio\n");
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else {
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gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
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platform_device_register(&smsc911x_device);
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}
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}
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static void __init mx31lite_timer_init(void)
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{
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mx31_clocks_init(26000000);
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}
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struct sys_timer mx31lite_timer = {
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.init = mx31lite_timer_init,
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};
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MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
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/* Maintainer: Freescale Semiconductor, Inc. */
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.atag_offset = 0x100,
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.map_io = mx31lite_map_io,
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.init_early = imx31_init_early,
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.init_irq = mx31_init_irq,
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.handle_irq = imx31_handle_irq,
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.timer = &mx31lite_timer,
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.init_machine = mx31lite_init,
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MACHINE_END
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