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5873d380f4
Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the IRQ_i_CFG register and requires a change of the driver to avoid writing into an undefined register address. Get the HW version from registers and set the IRQ_ENABLE bit to the correct register depending on the HW version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230905-topic-sm8x50-upstream-pdc-ver-v4-1-fc633c7df84b@linaro.org
374 lines
9.4 KiB
C
374 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/soc/qcom/irq.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#define PDC_MAX_GPIO_IRQS 256
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/* Valid only on HW version < 3.2 */
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#define IRQ_ENABLE_BANK 0x10
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#define IRQ_i_CFG 0x110
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/* Valid only on HW version >= 3.2 */
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#define IRQ_i_CFG_IRQ_ENABLE 3
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#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0)
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#define PDC_VERSION_REG 0x1000
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/* Notable PDC versions */
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#define PDC_VERSION_3_2 0x30200
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struct pdc_pin_region {
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u32 pin_base;
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u32 parent_base;
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u32 cnt;
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};
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#define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
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static DEFINE_RAW_SPINLOCK(pdc_lock);
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static void __iomem *pdc_base;
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static struct pdc_pin_region *pdc_region;
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static int pdc_region_cnt;
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static unsigned int pdc_version;
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static void pdc_reg_write(int reg, u32 i, u32 val)
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{
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writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
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}
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static u32 pdc_reg_read(int reg, u32 i)
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{
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return readl_relaxed(pdc_base + reg + i * sizeof(u32));
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}
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static void __pdc_enable_intr(int pin_out, bool on)
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{
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unsigned long enable;
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if (pdc_version < PDC_VERSION_3_2) {
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u32 index, mask;
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index = pin_out / 32;
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mask = pin_out % 32;
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enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
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__assign_bit(mask, &enable, on);
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pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
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} else {
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enable = pdc_reg_read(IRQ_i_CFG, pin_out);
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__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
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pdc_reg_write(IRQ_i_CFG, pin_out, enable);
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}
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}
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static void pdc_enable_intr(struct irq_data *d, bool on)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&pdc_lock, flags);
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__pdc_enable_intr(d->hwirq, on);
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raw_spin_unlock_irqrestore(&pdc_lock, flags);
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}
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static void qcom_pdc_gic_disable(struct irq_data *d)
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{
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pdc_enable_intr(d, false);
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irq_chip_disable_parent(d);
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}
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static void qcom_pdc_gic_enable(struct irq_data *d)
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{
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pdc_enable_intr(d, true);
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irq_chip_enable_parent(d);
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}
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/*
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* GIC does not handle falling edge or active low. To allow falling edge and
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* active low interrupts to be handled at GIC, PDC has an inverter that inverts
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* falling edge into a rising edge and active low into an active high.
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* For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
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* set as per the table below.
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* Level sensitive active low LOW
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* Rising edge sensitive NOT USED
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* Falling edge sensitive LOW
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* Dual Edge sensitive NOT USED
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* Level sensitive active High HIGH
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* Falling Edge sensitive NOT USED
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* Rising edge sensitive HIGH
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* Dual Edge sensitive HIGH
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*/
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enum pdc_irq_config_bits {
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PDC_LEVEL_LOW = 0b000,
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PDC_EDGE_FALLING = 0b010,
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PDC_LEVEL_HIGH = 0b100,
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PDC_EDGE_RISING = 0b110,
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PDC_EDGE_DUAL = 0b111,
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};
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/**
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* qcom_pdc_gic_set_type: Configure PDC for the interrupt
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*
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* @d: the interrupt data
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* @type: the interrupt type
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*
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* If @type is edge triggered, forward that as Rising edge as PDC
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* takes care of converting falling edge to rising edge signal
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* If @type is level, then forward that as level high as PDC
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* takes care of converting falling edge to rising edge signal
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*/
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static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
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{
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enum pdc_irq_config_bits pdc_type;
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enum pdc_irq_config_bits old_pdc_type;
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int ret;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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pdc_type = PDC_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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pdc_type = PDC_EDGE_FALLING;
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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pdc_type = PDC_EDGE_DUAL;
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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pdc_type = PDC_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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pdc_type = PDC_LEVEL_LOW;
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type = IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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WARN_ON(1);
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return -EINVAL;
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}
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old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
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pdc_type |= (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK);
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pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
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ret = irq_chip_set_type_parent(d, type);
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if (ret)
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return ret;
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/*
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* When we change types the PDC can give a phantom interrupt.
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* Clear it. Specifically the phantom shows up when reconfiguring
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* polarity of interrupt without changing the state of the signal
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* but let's be consistent and clear it always.
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*
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* Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
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* interrupt will be cleared before the rest of the system sees it.
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*/
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if (old_pdc_type != pdc_type)
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irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
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return 0;
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}
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static struct irq_chip qcom_pdc_gic_chip = {
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.name = "PDC",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_disable = qcom_pdc_gic_disable,
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.irq_enable = qcom_pdc_gic_enable,
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.irq_get_irqchip_state = irq_chip_get_parent_state,
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.irq_set_irqchip_state = irq_chip_set_parent_state,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = qcom_pdc_gic_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
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.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static struct pdc_pin_region *get_pin_region(int pin)
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{
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int i;
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for (i = 0; i < pdc_region_cnt; i++) {
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if (pin >= pdc_region[i].pin_base &&
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pin < pdc_region[i].pin_base + pdc_region[i].cnt)
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return &pdc_region[i];
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}
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return NULL;
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}
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static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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struct pdc_pin_region *region;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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if (hwirq == GPIO_NO_WAKE_IRQ)
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return irq_domain_disconnect_hierarchy(domain, virq);
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&qcom_pdc_gic_chip, NULL);
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if (ret)
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return ret;
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region = get_pin_region(hwirq);
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if (!region)
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return irq_domain_disconnect_hierarchy(domain->parent, virq);
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if (type & IRQ_TYPE_EDGE_BOTH)
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type = IRQ_TYPE_EDGE_RISING;
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if (type & IRQ_TYPE_LEVEL_MASK)
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type = IRQ_TYPE_LEVEL_HIGH;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = 0;
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parent_fwspec.param[1] = pin_to_hwirq(region, hwirq);
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parent_fwspec.param[2] = type;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops qcom_pdc_ops = {
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.translate = irq_domain_translate_twocell,
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.alloc = qcom_pdc_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int pdc_setup_pin_mapping(struct device_node *np)
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{
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int ret, n, i;
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n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
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if (n <= 0 || n % 3)
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return -EINVAL;
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pdc_region_cnt = n / 3;
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pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
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if (!pdc_region) {
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pdc_region_cnt = 0;
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return -ENOMEM;
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}
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for (n = 0; n < pdc_region_cnt; n++) {
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ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
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n * 3 + 0,
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&pdc_region[n].pin_base);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
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n * 3 + 1,
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&pdc_region[n].parent_base);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
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n * 3 + 2,
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&pdc_region[n].cnt);
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if (ret)
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return ret;
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for (i = 0; i < pdc_region[n].cnt; i++)
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__pdc_enable_intr(i + pdc_region[n].pin_base, 0);
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}
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return 0;
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}
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#define QCOM_PDC_SIZE 0x30000
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static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *parent_domain, *pdc_domain;
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resource_size_t res_size;
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struct resource res;
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int ret;
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/* compat with old sm8150 DT which had very small region for PDC */
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if (of_address_to_resource(node, 0, &res))
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return -EINVAL;
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res_size = max_t(resource_size_t, resource_size(&res), QCOM_PDC_SIZE);
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if (res_size > resource_size(&res))
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pr_warn("%pOF: invalid reg size, please fix DT\n", node);
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pdc_base = ioremap(res.start, res_size);
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if (!pdc_base) {
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pr_err("%pOF: unable to map PDC registers\n", node);
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return -ENXIO;
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}
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pdc_version = pdc_reg_read(PDC_VERSION_REG, 0);
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: unable to find PDC's parent domain\n", node);
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ret = -ENXIO;
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goto fail;
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}
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ret = pdc_setup_pin_mapping(node);
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if (ret) {
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pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
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goto fail;
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}
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pdc_domain = irq_domain_create_hierarchy(parent_domain,
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IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
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PDC_MAX_GPIO_IRQS,
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of_fwnode_handle(node),
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&qcom_pdc_ops, NULL);
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if (!pdc_domain) {
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pr_err("%pOF: PDC domain add failed\n", node);
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ret = -ENOMEM;
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goto fail;
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}
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irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP);
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return 0;
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fail:
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kfree(pdc_region);
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iounmap(pdc_base);
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return ret;
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}
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IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
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IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
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IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
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MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
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MODULE_LICENSE("GPL v2");
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