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21b2cec61c
This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v4.4 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # SH_MMCIF Tested-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200903162412.1.Id501e96fa63224f77bb86b2135a5e8324ffb9c43@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
481 lines
14 KiB
C
481 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Atmel SDMMC controller driver.
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include "sdhci-pltfm.h"
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#define SDMMC_MC1R 0x204
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#define SDMMC_MC1R_DDR BIT(3)
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#define SDMMC_MC1R_FCD BIT(7)
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#define SDMMC_CACR 0x230
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#define SDMMC_CACR_CAPWREN BIT(0)
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#define SDMMC_CACR_KEY (0x46 << 8)
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#define SDMMC_CALCR 0x240
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#define SDMMC_CALCR_EN BIT(0)
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#define SDMMC_CALCR_ALWYSON BIT(4)
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#define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
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struct sdhci_at91_soc_data {
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const struct sdhci_pltfm_data *pdata;
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bool baseclk_is_generated_internally;
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unsigned int divider_for_baseclk;
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};
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struct sdhci_at91_priv {
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const struct sdhci_at91_soc_data *soc_data;
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struct clk *hclock;
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struct clk *gck;
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struct clk *mainck;
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bool restore_needed;
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bool cal_always_on;
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};
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static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
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{
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u8 mc1r;
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mc1r = readb(host->ioaddr + SDMMC_MC1R);
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mc1r |= SDMMC_MC1R_FCD;
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writeb(mc1r, host->ioaddr + SDMMC_MC1R);
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}
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static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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u16 clk;
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unsigned long timeout;
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host->mmc->actual_clock = 0;
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/*
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* There is no requirement to disable the internal clock before
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* changing the SD clock configuration. Moreover, disabling the
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* internal clock, changing the configuration and re-enabling the
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* internal clock causes some bugs. It can prevent to get the internal
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* clock stable flag ready and an unexpected switch to the base clock
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* when using presets.
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*/
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return;
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clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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clk |= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Wait max 20 ms */
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timeout = 20;
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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pr_err("%s: Internal clock never stabilised.\n",
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mmc_hostname(host->mmc));
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return;
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}
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timeout--;
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mdelay(1);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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if (timing == MMC_TIMING_MMC_DDR52)
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sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
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sdhci_set_uhs_signaling(host, timing);
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}
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static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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sdhci_reset(host, mask);
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if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
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|| mmc_gpio_get_cd(host->mmc) >= 0)
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sdhci_at91_set_force_card_detect(host);
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if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) {
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u32 calcr = sdhci_readl(host, SDMMC_CALCR);
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sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
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SDMMC_CALCR);
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}
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}
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static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
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.set_clock = sdhci_at91_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_at91_reset,
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.set_uhs_signaling = sdhci_at91_set_uhs_signaling,
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.set_power = sdhci_set_power_and_bus_voltage,
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};
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static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = {
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.ops = &sdhci_at91_sama5d2_ops,
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};
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static const struct sdhci_at91_soc_data soc_data_sama5d2 = {
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.pdata = &sdhci_sama5d2_pdata,
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.baseclk_is_generated_internally = false,
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};
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static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
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.pdata = &sdhci_sama5d2_pdata,
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.baseclk_is_generated_internally = true,
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.divider_for_baseclk = 2,
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};
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static const struct of_device_id sdhci_at91_dt_match[] = {
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{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
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{ .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
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{}
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};
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MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
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static int sdhci_at91_set_clks_presets(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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unsigned int caps0, caps1;
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unsigned int clk_base, clk_mul;
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unsigned int gck_rate, clk_base_rate;
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unsigned int preset_div;
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clk_prepare_enable(priv->hclock);
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caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
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caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
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gck_rate = clk_get_rate(priv->gck);
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if (priv->soc_data->baseclk_is_generated_internally)
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clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk;
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else
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clk_base_rate = clk_get_rate(priv->mainck);
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clk_base = clk_base_rate / 1000000;
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clk_mul = gck_rate / clk_base_rate - 1;
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caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK;
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caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base);
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caps1 &= ~SDHCI_CLOCK_MUL_MASK;
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caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul);
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/* Set capabilities in r/w mode. */
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writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
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writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
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writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
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/* Set capabilities in ro mode. */
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writel(0, host->ioaddr + SDMMC_CACR);
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dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n",
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clk_mul, gck_rate, clk_base_rate);
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/*
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* We have to set preset values because it depends on the clk_mul
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* value. Moreover, SDR104 is supported in a degraded mode since the
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* maximum sd clock value is 120 MHz instead of 208 MHz. For that
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* reason, we need to use presets to support SDR104.
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*/
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preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR12);
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preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR25);
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preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR50);
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preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR104);
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preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_DDR50);
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clk_prepare_enable(priv->mainck);
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clk_prepare_enable(priv->gck);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int sdhci_at91_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = pm_runtime_force_suspend(dev);
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priv->restore_needed = true;
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return ret;
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}
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#endif /* CONFIG_PM_SLEEP */
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#ifdef CONFIG_PM
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static int sdhci_at91_runtime_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = sdhci_runtime_suspend_host(host);
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if (host->tuning_mode != SDHCI_TUNING_MODE_3)
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mmc_retune_needed(host->mmc);
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clk_disable_unprepare(priv->gck);
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clk_disable_unprepare(priv->hclock);
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clk_disable_unprepare(priv->mainck);
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return ret;
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}
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static int sdhci_at91_runtime_resume(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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if (priv->restore_needed) {
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ret = sdhci_at91_set_clks_presets(dev);
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if (ret)
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return ret;
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priv->restore_needed = false;
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goto out;
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}
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ret = clk_prepare_enable(priv->mainck);
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if (ret) {
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dev_err(dev, "can't enable mainck\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->hclock);
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if (ret) {
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dev_err(dev, "can't enable hclock\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->gck);
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if (ret) {
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dev_err(dev, "can't enable gck\n");
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return ret;
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}
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out:
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return sdhci_runtime_resume_host(host, 0);
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}
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#endif /* CONFIG_PM */
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static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
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sdhci_at91_runtime_resume,
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NULL)
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};
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static int sdhci_at91_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct sdhci_at91_soc_data *soc_data;
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_at91_priv *priv;
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int ret;
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match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
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if (!match)
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return -EINVAL;
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soc_data = match->data;
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host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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priv = sdhci_pltfm_priv(pltfm_host);
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priv->soc_data = soc_data;
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priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
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if (IS_ERR(priv->mainck)) {
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if (soc_data->baseclk_is_generated_internally) {
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priv->mainck = NULL;
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} else {
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dev_err(&pdev->dev, "failed to get baseclk\n");
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ret = PTR_ERR(priv->mainck);
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goto sdhci_pltfm_free;
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}
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}
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priv->hclock = devm_clk_get(&pdev->dev, "hclock");
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if (IS_ERR(priv->hclock)) {
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dev_err(&pdev->dev, "failed to get hclock\n");
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ret = PTR_ERR(priv->hclock);
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goto sdhci_pltfm_free;
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}
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priv->gck = devm_clk_get(&pdev->dev, "multclk");
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if (IS_ERR(priv->gck)) {
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dev_err(&pdev->dev, "failed to get multclk\n");
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ret = PTR_ERR(priv->gck);
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goto sdhci_pltfm_free;
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}
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ret = sdhci_at91_set_clks_presets(&pdev->dev);
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if (ret)
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goto sdhci_pltfm_free;
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priv->restore_needed = false;
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/*
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* if SDCAL pin is wrongly connected, we must enable
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* the analog calibration cell permanently.
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*/
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priv->cal_always_on =
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device_property_read_bool(&pdev->dev,
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"microchip,sdcal-inverted");
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto clocks_disable_unprepare;
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sdhci_get_of_property(pdev);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
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pm_runtime_use_autosuspend(&pdev->dev);
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/* HS200 is broken at this moment */
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host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
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ret = sdhci_add_host(host);
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if (ret)
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goto pm_runtime_disable;
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/*
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* When calling sdhci_runtime_suspend_host(), the sdhci layer makes
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* the assumption that all the clocks of the controller are disabled.
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* It means we can't get irq from it when it is runtime suspended.
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* For that reason, it is not planned to wake-up on a card detect irq
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* from the controller.
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* If we want to use runtime PM and to be able to wake-up on card
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* insertion, we have to use a GPIO for the card detection or we can
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* use polling. Be aware that using polling will resume/suspend the
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* controller between each attempt.
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* Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
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* to enable polling via device tree with broken-cd property.
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*/
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if (mmc_card_is_removable(host->mmc) &&
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mmc_gpio_get_cd(host->mmc) < 0) {
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host->mmc->caps |= MMC_CAP_NEEDS_POLL;
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host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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}
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/*
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* If the device attached to the MMC bus is not removable, it is safer
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* to set the Force Card Detect bit. People often don't connect the
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* card detect signal and use this pin for another purpose. If the card
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* detect pin is not muxed to SDHCI controller, a default value is
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* used. This value can be different from a SoC revision to another
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* one. Problems come when this default value is not card present. To
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* avoid this case, if the device is non removable then the card
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* detection procedure using the SDMCC_CD signal is bypassed.
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* This bit is reset when a software reset for all command is performed
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* so we need to implement our own reset function to set back this bit.
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*
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* WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
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*/
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if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
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|| mmc_gpio_get_cd(host->mmc) >= 0)
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sdhci_at91_set_force_card_detect(host);
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pm_runtime_put_autosuspend(&pdev->dev);
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return 0;
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pm_runtime_disable:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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clocks_disable_unprepare:
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clk_disable_unprepare(priv->gck);
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clk_disable_unprepare(priv->mainck);
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clk_disable_unprepare(priv->hclock);
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sdhci_pltfm_free:
|
|
sdhci_pltfm_free(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_at91_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct clk *gck = priv->gck;
|
|
struct clk *hclock = priv->hclock;
|
|
struct clk *mainck = priv->mainck;
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
sdhci_pltfm_unregister(pdev);
|
|
|
|
clk_disable_unprepare(gck);
|
|
clk_disable_unprepare(hclock);
|
|
clk_disable_unprepare(mainck);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdhci_at91_driver = {
|
|
.driver = {
|
|
.name = "sdhci-at91",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.of_match_table = sdhci_at91_dt_match,
|
|
.pm = &sdhci_at91_dev_pm_ops,
|
|
},
|
|
.probe = sdhci_at91_probe,
|
|
.remove = sdhci_at91_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_at91_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI driver for at91");
|
|
MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
|
|
MODULE_LICENSE("GPL v2");
|