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63a6ef2360
Add clock, memory controller, powergate and reset dt-binding headers for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
25 lines
857 B
C
25 lines
857 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
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#define __ABI_MACH_T234_POWERGATE_T234_H_
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#define TEGRA234_POWER_DOMAIN_AUD 2U
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#define TEGRA234_POWER_DOMAIN_DISP 3U
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#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U
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#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U
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#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U
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#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U
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#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U
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#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U
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#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U
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#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U
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#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U
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#define TEGRA234_POWER_DOMAIN_MGBEA 17U
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#define TEGRA234_POWER_DOMAIN_MGBEB 18U
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#define TEGRA234_POWER_DOMAIN_MGBEC 19U
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#define TEGRA234_POWER_DOMAIN_MGBED 20U
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#define TEGRA234_POWER_DOMAIN_VIC 29U
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#endif
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