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d86472ae8b
This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v5.4 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200903162412.5.I2b630c4d40ff4ea61d5b30b8ccfe95890e257100@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
1190 lines
29 KiB
C
1190 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
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*
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* Driver for Alcor Micro AU6601 and AU6621 controllers
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*/
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/* Note: this driver was created without any documentation. Based
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* on sniffing, testing and in some cases mimic of original driver.
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* As soon as some one with documentation or more experience in SD/MMC, or
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* reverse engineering then me, please review this driver and question every
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* thing what I did. 2018 Oleksij Rempel <linux@rempel-privat.de>
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/pm.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/alcor_pci.h>
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enum alcor_cookie {
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COOKIE_UNMAPPED,
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COOKIE_PRE_MAPPED,
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COOKIE_MAPPED,
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};
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struct alcor_pll_conf {
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unsigned int clk_src_freq;
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unsigned int clk_src_reg;
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unsigned int min_div;
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unsigned int max_div;
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};
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struct alcor_sdmmc_host {
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struct device *dev;
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struct alcor_pci_priv *alcor_pci;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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unsigned int dma_on:1;
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struct mutex cmd_mutex;
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struct delayed_work timeout_work;
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struct sg_mapping_iter sg_miter; /* SG state for PIO */
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struct scatterlist *sg;
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unsigned int blocks; /* remaining PIO blocks */
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int sg_count;
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u32 irq_status_sd;
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unsigned char cur_power_mode;
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};
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static const struct alcor_pll_conf alcor_pll_cfg[] = {
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/* MHZ, CLK src, max div, min div */
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{ 31250000, AU6601_CLK_31_25_MHZ, 1, 511},
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{ 48000000, AU6601_CLK_48_MHZ, 1, 511},
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{125000000, AU6601_CLK_125_MHZ, 1, 511},
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{384000000, AU6601_CLK_384_MHZ, 1, 511},
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};
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static inline void alcor_rmw8(struct alcor_sdmmc_host *host, unsigned int addr,
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u8 clear, u8 set)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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u32 var;
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var = alcor_read8(priv, addr);
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var &= ~clear;
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var |= set;
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alcor_write8(priv, var, addr);
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}
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/* As soon as irqs are masked, some status updates may be missed.
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* Use this with care.
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*/
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static inline void alcor_mask_sd_irqs(struct alcor_sdmmc_host *host)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
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}
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static inline void alcor_unmask_sd_irqs(struct alcor_sdmmc_host *host)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
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AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
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AU6601_INT_OVER_CURRENT_ERR,
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AU6601_REG_INT_ENABLE);
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}
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static void alcor_reset(struct alcor_sdmmc_host *host, u8 val)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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int i;
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alcor_write8(priv, val | AU6601_BUF_CTRL_RESET,
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AU6601_REG_SW_RESET);
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for (i = 0; i < 100; i++) {
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if (!(alcor_read8(priv, AU6601_REG_SW_RESET) & val))
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return;
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udelay(50);
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}
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dev_err(host->dev, "%s: timeout\n", __func__);
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}
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/*
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* Perform DMA I/O of a single page.
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*/
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static void alcor_data_set_dma(struct alcor_sdmmc_host *host)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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u32 addr;
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if (!host->sg_count)
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return;
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if (!host->sg) {
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dev_err(host->dev, "have blocks, but no SG\n");
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return;
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}
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if (!sg_dma_len(host->sg)) {
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dev_err(host->dev, "DMA SG len == 0\n");
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return;
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}
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addr = (u32)sg_dma_address(host->sg);
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alcor_write32(priv, addr, AU6601_REG_SDMA_ADDR);
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host->sg = sg_next(host->sg);
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host->sg_count--;
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}
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static void alcor_trigger_data_transfer(struct alcor_sdmmc_host *host)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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struct mmc_data *data = host->data;
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u8 ctrl = 0;
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if (data->flags & MMC_DATA_WRITE)
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ctrl |= AU6601_DATA_WRITE;
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if (data->host_cookie == COOKIE_MAPPED) {
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/*
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* For DMA transfers, this function is called just once,
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* at the start of the operation. The hardware can only
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* perform DMA I/O on a single page at a time, so here
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* we kick off the transfer with the first page, and expect
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* subsequent pages to be transferred upon IRQ events
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* indicating that the single-page DMA was completed.
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*/
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alcor_data_set_dma(host);
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ctrl |= AU6601_DATA_DMA_MODE;
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host->dma_on = 1;
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alcor_write32(priv, data->sg_count * 0x1000,
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AU6601_REG_BLOCK_SIZE);
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} else {
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/*
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* For PIO transfers, we break down each operation
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* into several sector-sized transfers. When one sector has
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* complete, the IRQ handler will call this function again
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* to kick off the transfer of the next sector.
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*/
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alcor_write32(priv, data->blksz, AU6601_REG_BLOCK_SIZE);
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}
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alcor_write8(priv, ctrl | AU6601_DATA_START_XFER,
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AU6601_DATA_XFER_CTRL);
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}
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static void alcor_trf_block_pio(struct alcor_sdmmc_host *host, bool read)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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size_t blksize, len;
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u8 *buf;
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if (!host->blocks)
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return;
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if (host->dma_on) {
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dev_err(host->dev, "configured DMA but got PIO request.\n");
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return;
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}
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if (!!(host->data->flags & MMC_DATA_READ) != read) {
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dev_err(host->dev, "got unexpected direction %i != %i\n",
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!!(host->data->flags & MMC_DATA_READ), read);
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}
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if (!sg_miter_next(&host->sg_miter))
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return;
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blksize = host->data->blksz;
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len = min(host->sg_miter.length, blksize);
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dev_dbg(host->dev, "PIO, %s block size: 0x%zx\n",
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read ? "read" : "write", blksize);
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host->sg_miter.consumed = len;
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host->blocks--;
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buf = host->sg_miter.addr;
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if (read)
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ioread32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2);
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else
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iowrite32_rep(priv->iobase + AU6601_REG_BUFFER, buf, len >> 2);
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sg_miter_stop(&host->sg_miter);
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}
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static void alcor_prepare_sg_miter(struct alcor_sdmmc_host *host)
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{
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unsigned int flags = SG_MITER_ATOMIC;
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struct mmc_data *data = host->data;
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if (data->flags & MMC_DATA_READ)
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flags |= SG_MITER_TO_SG;
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else
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flags |= SG_MITER_FROM_SG;
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sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
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}
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static void alcor_prepare_data(struct alcor_sdmmc_host *host,
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struct mmc_command *cmd)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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struct mmc_data *data = cmd->data;
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if (!data)
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return;
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host->data = data;
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host->data->bytes_xfered = 0;
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host->blocks = data->blocks;
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host->sg = data->sg;
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host->sg_count = data->sg_count;
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dev_dbg(host->dev, "prepare DATA: sg %i, blocks: %i\n",
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host->sg_count, host->blocks);
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if (data->host_cookie != COOKIE_MAPPED)
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alcor_prepare_sg_miter(host);
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alcor_write8(priv, 0, AU6601_DATA_XFER_CTRL);
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}
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static void alcor_send_cmd(struct alcor_sdmmc_host *host,
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struct mmc_command *cmd, bool set_timeout)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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unsigned long timeout = 0;
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u8 ctrl = 0;
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host->cmd = cmd;
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alcor_prepare_data(host, cmd);
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dev_dbg(host->dev, "send CMD. opcode: 0x%02x, arg; 0x%08x\n",
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cmd->opcode, cmd->arg);
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alcor_write8(priv, cmd->opcode | 0x40, AU6601_REG_CMD_OPCODE);
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alcor_write32be(priv, cmd->arg, AU6601_REG_CMD_ARG);
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switch (mmc_resp_type(cmd)) {
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case MMC_RSP_NONE:
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ctrl = AU6601_CMD_NO_RESP;
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break;
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case MMC_RSP_R1:
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ctrl = AU6601_CMD_6_BYTE_CRC;
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break;
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case MMC_RSP_R1B:
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ctrl = AU6601_CMD_6_BYTE_CRC | AU6601_CMD_STOP_WAIT_RDY;
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break;
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case MMC_RSP_R2:
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ctrl = AU6601_CMD_17_BYTE_CRC;
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break;
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case MMC_RSP_R3:
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ctrl = AU6601_CMD_6_BYTE_WO_CRC;
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break;
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default:
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dev_err(host->dev, "%s: cmd->flag (0x%02x) is not valid\n",
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mmc_hostname(mmc_from_priv(host)), mmc_resp_type(cmd));
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break;
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}
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if (set_timeout) {
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if (!cmd->data && cmd->busy_timeout)
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timeout = cmd->busy_timeout;
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else
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timeout = 10000;
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schedule_delayed_work(&host->timeout_work,
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msecs_to_jiffies(timeout));
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}
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dev_dbg(host->dev, "xfer ctrl: 0x%02x; timeout: %lu\n", ctrl, timeout);
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alcor_write8(priv, ctrl | AU6601_CMD_START_XFER,
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AU6601_CMD_XFER_CTRL);
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}
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static void alcor_request_complete(struct alcor_sdmmc_host *host,
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bool cancel_timeout)
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{
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struct mmc_request *mrq;
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/*
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* If this work gets rescheduled while running, it will
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* be run again afterwards but without any active request.
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*/
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if (!host->mrq)
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return;
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if (cancel_timeout)
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cancel_delayed_work(&host->timeout_work);
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mrq = host->mrq;
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host->mrq = NULL;
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host->cmd = NULL;
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host->data = NULL;
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host->dma_on = 0;
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mmc_request_done(mmc_from_priv(host), mrq);
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}
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static void alcor_finish_data(struct alcor_sdmmc_host *host)
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{
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struct mmc_data *data;
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data = host->data;
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host->data = NULL;
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host->dma_on = 0;
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/*
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* The specification states that the block count register must
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* be updated, but it does not specify at what point in the
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* data flow. That makes the register entirely useless to read
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* back so we have to assume that nothing made it to the card
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* in the event of an error.
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*/
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if (data->error)
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data->bytes_xfered = 0;
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else
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data->bytes_xfered = data->blksz * data->blocks;
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/*
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* Need to send CMD12 if -
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* a) open-ended multiblock transfer (no CMD23)
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* b) error in multiblock transfer
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*/
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if (data->stop &&
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(data->error ||
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!host->mrq->sbc)) {
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/*
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* The controller needs a reset of internal state machines
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* upon error conditions.
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*/
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if (data->error)
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alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
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alcor_unmask_sd_irqs(host);
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alcor_send_cmd(host, data->stop, false);
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return;
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}
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alcor_request_complete(host, 1);
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}
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static void alcor_err_irq(struct alcor_sdmmc_host *host, u32 intmask)
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{
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dev_dbg(host->dev, "ERR IRQ %x\n", intmask);
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if (host->cmd) {
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if (intmask & AU6601_INT_CMD_TIMEOUT_ERR)
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host->cmd->error = -ETIMEDOUT;
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else
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host->cmd->error = -EILSEQ;
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}
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if (host->data) {
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if (intmask & AU6601_INT_DATA_TIMEOUT_ERR)
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host->data->error = -ETIMEDOUT;
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else
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host->data->error = -EILSEQ;
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host->data->bytes_xfered = 0;
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}
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alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
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alcor_request_complete(host, 1);
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}
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static int alcor_cmd_irq_done(struct alcor_sdmmc_host *host, u32 intmask)
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{
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struct alcor_pci_priv *priv = host->alcor_pci;
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intmask &= AU6601_INT_CMD_END;
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if (!intmask)
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return true;
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/* got CMD_END but no CMD is in progress, wake thread an process the
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* error
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*/
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if (!host->cmd)
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return false;
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if (host->cmd->flags & MMC_RSP_PRESENT) {
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struct mmc_command *cmd = host->cmd;
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cmd->resp[0] = alcor_read32be(priv, AU6601_REG_CMD_RSP0);
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dev_dbg(host->dev, "RSP0: 0x%04x\n", cmd->resp[0]);
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if (host->cmd->flags & MMC_RSP_136) {
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cmd->resp[1] =
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alcor_read32be(priv, AU6601_REG_CMD_RSP1);
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cmd->resp[2] =
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alcor_read32be(priv, AU6601_REG_CMD_RSP2);
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cmd->resp[3] =
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alcor_read32be(priv, AU6601_REG_CMD_RSP3);
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dev_dbg(host->dev, "RSP1,2,3: 0x%04x 0x%04x 0x%04x\n",
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cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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}
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host->cmd->error = 0;
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/* Processed actual command. */
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if (!host->data)
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return false;
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alcor_trigger_data_transfer(host);
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host->cmd = NULL;
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return true;
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}
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static void alcor_cmd_irq_thread(struct alcor_sdmmc_host *host, u32 intmask)
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{
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intmask &= AU6601_INT_CMD_END;
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if (!intmask)
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return;
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if (!host->cmd && intmask & AU6601_INT_CMD_END) {
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dev_dbg(host->dev, "Got command interrupt 0x%08x even though no command operation was in progress.\n",
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intmask);
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}
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/* Processed actual command. */
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if (!host->data)
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alcor_request_complete(host, 1);
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else
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alcor_trigger_data_transfer(host);
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host->cmd = NULL;
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}
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static int alcor_data_irq_done(struct alcor_sdmmc_host *host, u32 intmask)
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{
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u32 tmp;
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intmask &= AU6601_INT_DATA_MASK;
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/* nothing here to do */
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if (!intmask)
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return 1;
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/* we was too fast and got DATA_END after it was processed?
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* lets ignore it for now.
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*/
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if (!host->data && intmask == AU6601_INT_DATA_END)
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return 1;
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/* looks like an error, so lets handle it. */
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if (!host->data)
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return 0;
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tmp = intmask & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY
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| AU6601_INT_DMA_END);
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switch (tmp) {
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case 0:
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break;
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case AU6601_INT_READ_BUF_RDY:
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alcor_trf_block_pio(host, true);
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return 1;
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case AU6601_INT_WRITE_BUF_RDY:
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alcor_trf_block_pio(host, false);
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return 1;
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case AU6601_INT_DMA_END:
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if (!host->sg_count)
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break;
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alcor_data_set_dma(host);
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break;
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default:
|
|
dev_err(host->dev, "Got READ_BUF_RDY and WRITE_BUF_RDY at same time\n");
|
|
break;
|
|
}
|
|
|
|
if (intmask & AU6601_INT_DATA_END) {
|
|
if (!host->dma_on && host->blocks) {
|
|
alcor_trigger_data_transfer(host);
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void alcor_data_irq_thread(struct alcor_sdmmc_host *host, u32 intmask)
|
|
{
|
|
intmask &= AU6601_INT_DATA_MASK;
|
|
|
|
if (!intmask)
|
|
return;
|
|
|
|
if (!host->data) {
|
|
dev_dbg(host->dev, "Got data interrupt 0x%08x even though no data operation was in progress.\n",
|
|
intmask);
|
|
alcor_reset(host, AU6601_RESET_DATA);
|
|
return;
|
|
}
|
|
|
|
if (alcor_data_irq_done(host, intmask))
|
|
return;
|
|
|
|
if ((intmask & AU6601_INT_DATA_END) || !host->blocks ||
|
|
(host->dma_on && !host->sg_count))
|
|
alcor_finish_data(host);
|
|
}
|
|
|
|
static void alcor_cd_irq(struct alcor_sdmmc_host *host, u32 intmask)
|
|
{
|
|
dev_dbg(host->dev, "card %s\n",
|
|
intmask & AU6601_INT_CARD_REMOVE ? "removed" : "inserted");
|
|
|
|
if (host->mrq) {
|
|
dev_dbg(host->dev, "cancel all pending tasks.\n");
|
|
|
|
if (host->data)
|
|
host->data->error = -ENOMEDIUM;
|
|
|
|
if (host->cmd)
|
|
host->cmd->error = -ENOMEDIUM;
|
|
else
|
|
host->mrq->cmd->error = -ENOMEDIUM;
|
|
|
|
alcor_request_complete(host, 1);
|
|
}
|
|
|
|
mmc_detect_change(mmc_from_priv(host), msecs_to_jiffies(1));
|
|
}
|
|
|
|
static irqreturn_t alcor_irq_thread(int irq, void *d)
|
|
{
|
|
struct alcor_sdmmc_host *host = d;
|
|
irqreturn_t ret = IRQ_HANDLED;
|
|
u32 intmask, tmp;
|
|
|
|
mutex_lock(&host->cmd_mutex);
|
|
|
|
intmask = host->irq_status_sd;
|
|
|
|
/* some thing bad */
|
|
if (unlikely(!intmask || AU6601_INT_ALL_MASK == intmask)) {
|
|
dev_dbg(host->dev, "unexpected IRQ: 0x%04x\n", intmask);
|
|
ret = IRQ_NONE;
|
|
goto exit;
|
|
}
|
|
|
|
tmp = intmask & (AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK);
|
|
if (tmp) {
|
|
if (tmp & AU6601_INT_ERROR_MASK)
|
|
alcor_err_irq(host, tmp);
|
|
else {
|
|
alcor_cmd_irq_thread(host, tmp);
|
|
alcor_data_irq_thread(host, tmp);
|
|
}
|
|
intmask &= ~(AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK);
|
|
}
|
|
|
|
if (intmask & (AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE)) {
|
|
alcor_cd_irq(host, intmask);
|
|
intmask &= ~(AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE);
|
|
}
|
|
|
|
if (intmask & AU6601_INT_OVER_CURRENT_ERR) {
|
|
dev_warn(host->dev,
|
|
"warning: over current detected!\n");
|
|
intmask &= ~AU6601_INT_OVER_CURRENT_ERR;
|
|
}
|
|
|
|
if (intmask)
|
|
dev_dbg(host->dev, "got not handled IRQ: 0x%04x\n", intmask);
|
|
|
|
exit:
|
|
mutex_unlock(&host->cmd_mutex);
|
|
alcor_unmask_sd_irqs(host);
|
|
return ret;
|
|
}
|
|
|
|
|
|
static irqreturn_t alcor_irq(int irq, void *d)
|
|
{
|
|
struct alcor_sdmmc_host *host = d;
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
u32 status, tmp;
|
|
irqreturn_t ret;
|
|
int cmd_done, data_done;
|
|
|
|
status = alcor_read32(priv, AU6601_REG_INT_STATUS);
|
|
if (!status)
|
|
return IRQ_NONE;
|
|
|
|
alcor_write32(priv, status, AU6601_REG_INT_STATUS);
|
|
|
|
tmp = status & (AU6601_INT_READ_BUF_RDY | AU6601_INT_WRITE_BUF_RDY
|
|
| AU6601_INT_DATA_END | AU6601_INT_DMA_END
|
|
| AU6601_INT_CMD_END);
|
|
if (tmp == status) {
|
|
cmd_done = alcor_cmd_irq_done(host, tmp);
|
|
data_done = alcor_data_irq_done(host, tmp);
|
|
/* use fast path for simple tasks */
|
|
if (cmd_done && data_done) {
|
|
ret = IRQ_HANDLED;
|
|
goto alcor_irq_done;
|
|
}
|
|
}
|
|
|
|
host->irq_status_sd = status;
|
|
ret = IRQ_WAKE_THREAD;
|
|
alcor_mask_sd_irqs(host);
|
|
alcor_irq_done:
|
|
return ret;
|
|
}
|
|
|
|
static void alcor_set_clock(struct alcor_sdmmc_host *host, unsigned int clock)
|
|
{
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
int i, diff = 0x7fffffff, tmp_clock = 0;
|
|
u16 clk_src = 0;
|
|
u8 clk_div = 0;
|
|
|
|
if (clock == 0) {
|
|
alcor_write16(priv, 0, AU6601_CLK_SELECT);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(alcor_pll_cfg); i++) {
|
|
unsigned int tmp_div, tmp_diff;
|
|
const struct alcor_pll_conf *cfg = &alcor_pll_cfg[i];
|
|
|
|
tmp_div = DIV_ROUND_UP(cfg->clk_src_freq, clock);
|
|
if (cfg->min_div > tmp_div || tmp_div > cfg->max_div)
|
|
continue;
|
|
|
|
tmp_clock = DIV_ROUND_UP(cfg->clk_src_freq, tmp_div);
|
|
tmp_diff = abs(clock - tmp_clock);
|
|
|
|
if (tmp_diff < diff) {
|
|
diff = tmp_diff;
|
|
clk_src = cfg->clk_src_reg;
|
|
clk_div = tmp_div;
|
|
}
|
|
}
|
|
|
|
clk_src |= ((clk_div - 1) << 8);
|
|
clk_src |= AU6601_CLK_ENABLE;
|
|
|
|
dev_dbg(host->dev, "set freq %d cal freq %d, use div %d, mod %x\n",
|
|
clock, tmp_clock, clk_div, clk_src);
|
|
|
|
alcor_write16(priv, clk_src, AU6601_CLK_SELECT);
|
|
|
|
}
|
|
|
|
static void alcor_set_timing(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
|
|
if (ios->timing == MMC_TIMING_LEGACY) {
|
|
alcor_rmw8(host, AU6601_CLK_DELAY,
|
|
AU6601_CLK_POSITIVE_EDGE_ALL, 0);
|
|
} else {
|
|
alcor_rmw8(host, AU6601_CLK_DELAY,
|
|
0, AU6601_CLK_POSITIVE_EDGE_ALL);
|
|
}
|
|
}
|
|
|
|
static void alcor_set_bus_width(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_1) {
|
|
alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
|
|
} else if (ios->bus_width == MMC_BUS_WIDTH_4) {
|
|
alcor_write8(priv, AU6601_BUS_WIDTH_4BIT,
|
|
AU6601_REG_BUS_CTRL);
|
|
} else
|
|
dev_err(host->dev, "Unknown BUS mode\n");
|
|
|
|
}
|
|
|
|
static int alcor_card_busy(struct mmc_host *mmc)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
u8 status;
|
|
|
|
/* Check whether dat[0:3] low */
|
|
status = alcor_read8(priv, AU6601_DATA_PIN_STATE);
|
|
|
|
return !(status & AU6601_BUS_STAT_DAT_MASK);
|
|
}
|
|
|
|
static int alcor_get_cd(struct mmc_host *mmc)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
u8 detect;
|
|
|
|
detect = alcor_read8(priv, AU6601_DETECT_STATUS)
|
|
& AU6601_DETECT_STATUS_M;
|
|
/* check if card is present then send command and data */
|
|
return (detect == AU6601_SD_DETECTED);
|
|
}
|
|
|
|
static int alcor_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
u8 status;
|
|
|
|
/* get write protect pin status */
|
|
status = alcor_read8(priv, AU6601_INTERFACE_MODE_CTRL);
|
|
|
|
return !!(status & AU6601_SD_CARD_WP);
|
|
}
|
|
|
|
static void alcor_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
|
|
mutex_lock(&host->cmd_mutex);
|
|
|
|
host->mrq = mrq;
|
|
|
|
/* check if card is present then send command and data */
|
|
if (alcor_get_cd(mmc))
|
|
alcor_send_cmd(host, mrq->cmd, true);
|
|
else {
|
|
mrq->cmd->error = -ENOMEDIUM;
|
|
alcor_request_complete(host, 1);
|
|
}
|
|
|
|
mutex_unlock(&host->cmd_mutex);
|
|
}
|
|
|
|
static void alcor_pre_req(struct mmc_host *mmc,
|
|
struct mmc_request *mrq)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct mmc_data *data = mrq->data;
|
|
struct mmc_command *cmd = mrq->cmd;
|
|
struct scatterlist *sg;
|
|
unsigned int i, sg_len;
|
|
|
|
if (!data || !cmd)
|
|
return;
|
|
|
|
data->host_cookie = COOKIE_UNMAPPED;
|
|
|
|
/* FIXME: looks like the DMA engine works only with CMD18 */
|
|
if (cmd->opcode != MMC_READ_MULTIPLE_BLOCK
|
|
&& cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK)
|
|
return;
|
|
/*
|
|
* We don't do DMA on "complex" transfers, i.e. with
|
|
* non-word-aligned buffers or lengths. A future improvement
|
|
* could be made to use temporary DMA bounce-buffers when these
|
|
* requirements are not met.
|
|
*
|
|
* Also, we don't bother with all the DMA setup overhead for
|
|
* short transfers.
|
|
*/
|
|
if (data->blocks * data->blksz < AU6601_MAX_DMA_BLOCK_SIZE)
|
|
return;
|
|
|
|
if (data->blksz & 3)
|
|
return;
|
|
|
|
for_each_sg(data->sg, sg, data->sg_len, i) {
|
|
if (sg->length != AU6601_MAX_DMA_BLOCK_SIZE)
|
|
return;
|
|
if (sg->offset != 0)
|
|
return;
|
|
}
|
|
|
|
/* This data might be unmapped at this time */
|
|
|
|
sg_len = dma_map_sg(host->dev, data->sg, data->sg_len,
|
|
mmc_get_dma_dir(data));
|
|
if (sg_len)
|
|
data->host_cookie = COOKIE_MAPPED;
|
|
|
|
data->sg_count = sg_len;
|
|
}
|
|
|
|
static void alcor_post_req(struct mmc_host *mmc,
|
|
struct mmc_request *mrq,
|
|
int err)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct mmc_data *data = mrq->data;
|
|
|
|
if (!data)
|
|
return;
|
|
|
|
if (data->host_cookie == COOKIE_MAPPED) {
|
|
dma_unmap_sg(host->dev,
|
|
data->sg,
|
|
data->sg_len,
|
|
mmc_get_dma_dir(data));
|
|
}
|
|
|
|
data->host_cookie = COOKIE_UNMAPPED;
|
|
}
|
|
|
|
static void alcor_set_power_mode(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
|
|
switch (ios->power_mode) {
|
|
case MMC_POWER_OFF:
|
|
alcor_set_clock(host, ios->clock);
|
|
/* set all pins to input */
|
|
alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
|
|
/* turn of VDD */
|
|
alcor_write8(priv, 0, AU6601_POWER_CONTROL);
|
|
break;
|
|
case MMC_POWER_UP:
|
|
break;
|
|
case MMC_POWER_ON:
|
|
/* This is most trickiest part. The order and timings of
|
|
* instructions seems to play important role. Any changes may
|
|
* confuse internal state engine if this HW.
|
|
* FIXME: If we will ever get access to documentation, then this
|
|
* part should be reviewed again.
|
|
*/
|
|
|
|
/* enable SD card mode */
|
|
alcor_write8(priv, AU6601_SD_CARD,
|
|
AU6601_ACTIVE_CTRL);
|
|
/* set signal voltage to 3.3V */
|
|
alcor_write8(priv, 0, AU6601_OPT);
|
|
/* no documentation about clk delay, for now just try to mimic
|
|
* original driver.
|
|
*/
|
|
alcor_write8(priv, 0x20, AU6601_CLK_DELAY);
|
|
/* set BUS width to 1 bit */
|
|
alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
|
|
/* set CLK first time */
|
|
alcor_set_clock(host, ios->clock);
|
|
/* power on VDD */
|
|
alcor_write8(priv, AU6601_SD_CARD,
|
|
AU6601_POWER_CONTROL);
|
|
/* wait until the CLK will get stable */
|
|
mdelay(20);
|
|
/* set CLK again, mimic original driver. */
|
|
alcor_set_clock(host, ios->clock);
|
|
|
|
/* enable output */
|
|
alcor_write8(priv, AU6601_SD_CARD,
|
|
AU6601_OUTPUT_ENABLE);
|
|
/* The clk will not work on au6621. We need to trigger data
|
|
* transfer.
|
|
*/
|
|
alcor_write8(priv, AU6601_DATA_WRITE,
|
|
AU6601_DATA_XFER_CTRL);
|
|
/* configure timeout. Not clear what exactly it means. */
|
|
alcor_write8(priv, 0x7d, AU6601_TIME_OUT_CTRL);
|
|
mdelay(100);
|
|
break;
|
|
default:
|
|
dev_err(host->dev, "Unknown power parameter\n");
|
|
}
|
|
}
|
|
|
|
static void alcor_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
|
|
mutex_lock(&host->cmd_mutex);
|
|
|
|
dev_dbg(host->dev, "set ios. bus width: %x, power mode: %x\n",
|
|
ios->bus_width, ios->power_mode);
|
|
|
|
if (ios->power_mode != host->cur_power_mode) {
|
|
alcor_set_power_mode(mmc, ios);
|
|
host->cur_power_mode = ios->power_mode;
|
|
} else {
|
|
alcor_set_timing(mmc, ios);
|
|
alcor_set_bus_width(mmc, ios);
|
|
alcor_set_clock(host, ios->clock);
|
|
}
|
|
|
|
mutex_unlock(&host->cmd_mutex);
|
|
}
|
|
|
|
static int alcor_signal_voltage_switch(struct mmc_host *mmc,
|
|
struct mmc_ios *ios)
|
|
{
|
|
struct alcor_sdmmc_host *host = mmc_priv(mmc);
|
|
|
|
mutex_lock(&host->cmd_mutex);
|
|
|
|
switch (ios->signal_voltage) {
|
|
case MMC_SIGNAL_VOLTAGE_330:
|
|
alcor_rmw8(host, AU6601_OPT, AU6601_OPT_SD_18V, 0);
|
|
break;
|
|
case MMC_SIGNAL_VOLTAGE_180:
|
|
alcor_rmw8(host, AU6601_OPT, 0, AU6601_OPT_SD_18V);
|
|
break;
|
|
default:
|
|
/* No signal voltage switch required */
|
|
break;
|
|
}
|
|
|
|
mutex_unlock(&host->cmd_mutex);
|
|
return 0;
|
|
}
|
|
|
|
static const struct mmc_host_ops alcor_sdc_ops = {
|
|
.card_busy = alcor_card_busy,
|
|
.get_cd = alcor_get_cd,
|
|
.get_ro = alcor_get_ro,
|
|
.post_req = alcor_post_req,
|
|
.pre_req = alcor_pre_req,
|
|
.request = alcor_request,
|
|
.set_ios = alcor_set_ios,
|
|
.start_signal_voltage_switch = alcor_signal_voltage_switch,
|
|
};
|
|
|
|
static void alcor_timeout_timer(struct work_struct *work)
|
|
{
|
|
struct delayed_work *d = to_delayed_work(work);
|
|
struct alcor_sdmmc_host *host = container_of(d, struct alcor_sdmmc_host,
|
|
timeout_work);
|
|
mutex_lock(&host->cmd_mutex);
|
|
|
|
dev_dbg(host->dev, "triggered timeout\n");
|
|
if (host->mrq) {
|
|
dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
|
|
|
|
if (host->data) {
|
|
host->data->error = -ETIMEDOUT;
|
|
} else {
|
|
if (host->cmd)
|
|
host->cmd->error = -ETIMEDOUT;
|
|
else
|
|
host->mrq->cmd->error = -ETIMEDOUT;
|
|
}
|
|
|
|
alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
|
|
alcor_request_complete(host, 0);
|
|
}
|
|
|
|
mutex_unlock(&host->cmd_mutex);
|
|
}
|
|
|
|
static void alcor_hw_init(struct alcor_sdmmc_host *host)
|
|
{
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
struct alcor_dev_cfg *cfg = priv->cfg;
|
|
|
|
/* FIXME: This part is a mimics HW init of original driver.
|
|
* If we will ever get access to documentation, then this part
|
|
* should be reviewed again.
|
|
*/
|
|
|
|
/* reset command state engine */
|
|
alcor_reset(host, AU6601_RESET_CMD);
|
|
|
|
alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
|
|
/* enable sd card mode */
|
|
alcor_write8(priv, AU6601_SD_CARD, AU6601_ACTIVE_CTRL);
|
|
|
|
/* set BUS width to 1 bit */
|
|
alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
|
|
|
|
/* reset data state engine */
|
|
alcor_reset(host, AU6601_RESET_DATA);
|
|
/* Not sure if a voodoo with AU6601_DMA_BOUNDARY is really needed */
|
|
alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
|
|
|
|
alcor_write8(priv, 0, AU6601_INTERFACE_MODE_CTRL);
|
|
/* not clear what we are doing here. */
|
|
alcor_write8(priv, 0x44, AU6601_PAD_DRIVE0);
|
|
alcor_write8(priv, 0x44, AU6601_PAD_DRIVE1);
|
|
alcor_write8(priv, 0x00, AU6601_PAD_DRIVE2);
|
|
|
|
/* for 6601 - dma_boundary; for 6621 - dma_page_cnt
|
|
* exact meaning of this register is not clear.
|
|
*/
|
|
alcor_write8(priv, cfg->dma, AU6601_DMA_BOUNDARY);
|
|
|
|
/* make sure all pins are set to input and VDD is off */
|
|
alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
|
|
alcor_write8(priv, 0, AU6601_POWER_CONTROL);
|
|
|
|
alcor_write8(priv, AU6601_DETECT_EN, AU6601_DETECT_STATUS);
|
|
/* now we should be safe to enable IRQs */
|
|
alcor_unmask_sd_irqs(host);
|
|
}
|
|
|
|
static void alcor_hw_uninit(struct alcor_sdmmc_host *host)
|
|
{
|
|
struct alcor_pci_priv *priv = host->alcor_pci;
|
|
|
|
alcor_mask_sd_irqs(host);
|
|
alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
|
|
|
|
alcor_write8(priv, 0, AU6601_DETECT_STATUS);
|
|
|
|
alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
|
|
alcor_write8(priv, 0, AU6601_POWER_CONTROL);
|
|
|
|
alcor_write8(priv, 0, AU6601_OPT);
|
|
}
|
|
|
|
static void alcor_init_mmc(struct alcor_sdmmc_host *host)
|
|
{
|
|
struct mmc_host *mmc = mmc_from_priv(host);
|
|
|
|
mmc->f_min = AU6601_MIN_CLOCK;
|
|
mmc->f_max = AU6601_MAX_CLOCK;
|
|
mmc->ocr_avail = MMC_VDD_33_34;
|
|
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED
|
|
| MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
|
|
| MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50;
|
|
mmc->caps2 = MMC_CAP2_NO_SDIO;
|
|
mmc->ops = &alcor_sdc_ops;
|
|
|
|
/* The hardware does DMA data transfer of 4096 bytes to/from a single
|
|
* buffer address. Scatterlists are not supported at the hardware
|
|
* level, however we can work with them at the driver level,
|
|
* provided that each segment is exactly 4096 bytes in size.
|
|
* Upon DMA completion of a single segment (signalled via IRQ), we
|
|
* immediately proceed to transfer the next segment from the
|
|
* scatterlist.
|
|
*
|
|
* The overall request is limited to 240 sectors, matching the
|
|
* original vendor driver.
|
|
*/
|
|
mmc->max_segs = AU6601_MAX_DMA_SEGMENTS;
|
|
mmc->max_seg_size = AU6601_MAX_DMA_BLOCK_SIZE;
|
|
mmc->max_blk_count = 240;
|
|
mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
|
|
dma_set_max_seg_size(host->dev, mmc->max_seg_size);
|
|
}
|
|
|
|
static int alcor_pci_sdmmc_drv_probe(struct platform_device *pdev)
|
|
{
|
|
struct alcor_pci_priv *priv = pdev->dev.platform_data;
|
|
struct mmc_host *mmc;
|
|
struct alcor_sdmmc_host *host;
|
|
int ret;
|
|
|
|
mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
|
|
if (!mmc) {
|
|
dev_err(&pdev->dev, "Can't allocate MMC\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
host = mmc_priv(mmc);
|
|
host->dev = &pdev->dev;
|
|
host->cur_power_mode = MMC_POWER_UNDEFINED;
|
|
host->alcor_pci = priv;
|
|
|
|
/* make sure irqs are disabled */
|
|
alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
|
|
alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
|
|
alcor_irq, alcor_irq_thread, IRQF_SHARED,
|
|
DRV_NAME_ALCOR_PCI_SDMMC, host);
|
|
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to get irq for data line\n");
|
|
goto free_host;
|
|
}
|
|
|
|
mutex_init(&host->cmd_mutex);
|
|
INIT_DELAYED_WORK(&host->timeout_work, alcor_timeout_timer);
|
|
|
|
alcor_init_mmc(host);
|
|
alcor_hw_init(host);
|
|
|
|
dev_set_drvdata(&pdev->dev, host);
|
|
mmc_add_host(mmc);
|
|
return 0;
|
|
|
|
free_host:
|
|
mmc_free_host(mmc);
|
|
return ret;
|
|
}
|
|
|
|
static int alcor_pci_sdmmc_drv_remove(struct platform_device *pdev)
|
|
{
|
|
struct alcor_sdmmc_host *host = dev_get_drvdata(&pdev->dev);
|
|
struct mmc_host *mmc = mmc_from_priv(host);
|
|
|
|
if (cancel_delayed_work_sync(&host->timeout_work))
|
|
alcor_request_complete(host, 0);
|
|
|
|
alcor_hw_uninit(host);
|
|
mmc_remove_host(mmc);
|
|
mmc_free_host(mmc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int alcor_pci_sdmmc_suspend(struct device *dev)
|
|
{
|
|
struct alcor_sdmmc_host *host = dev_get_drvdata(dev);
|
|
|
|
if (cancel_delayed_work_sync(&host->timeout_work))
|
|
alcor_request_complete(host, 0);
|
|
|
|
alcor_hw_uninit(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int alcor_pci_sdmmc_resume(struct device *dev)
|
|
{
|
|
struct alcor_sdmmc_host *host = dev_get_drvdata(dev);
|
|
|
|
alcor_hw_init(host);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static SIMPLE_DEV_PM_OPS(alcor_mmc_pm_ops, alcor_pci_sdmmc_suspend,
|
|
alcor_pci_sdmmc_resume);
|
|
|
|
static const struct platform_device_id alcor_pci_sdmmc_ids[] = {
|
|
{
|
|
.name = DRV_NAME_ALCOR_PCI_SDMMC,
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, alcor_pci_sdmmc_ids);
|
|
|
|
static struct platform_driver alcor_pci_sdmmc_driver = {
|
|
.probe = alcor_pci_sdmmc_drv_probe,
|
|
.remove = alcor_pci_sdmmc_drv_remove,
|
|
.id_table = alcor_pci_sdmmc_ids,
|
|
.driver = {
|
|
.name = DRV_NAME_ALCOR_PCI_SDMMC,
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.pm = &alcor_mmc_pm_ops
|
|
},
|
|
};
|
|
module_platform_driver(alcor_pci_sdmmc_driver);
|
|
|
|
MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
|
|
MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
|
|
MODULE_LICENSE("GPL");
|