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35959958df
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. In v6.5 it has also acquired the ability to generate multi-register writes in sync operations, bringing performance up to parity with the rbtree cache there. Update the sta529 driver to use the more modern data structure. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230712-asoc-st-maple-v1-3-46eab2c0ce23@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
391 lines
9.6 KiB
C
391 lines
9.6 KiB
C
/*
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* ASoC codec driver for spear platform
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*
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* sound/soc/codecs/sta529.c -- spear ALSA Soc codec driver
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*
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* Copyright (C) 2012 ST Microelectronics
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* Rajeev Kumar <rajeevkumar.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include <sound/tlv.h>
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/* STA529 Register offsets */
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#define STA529_FFXCFG0 0x00
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#define STA529_FFXCFG1 0x01
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#define STA529_MVOL 0x02
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#define STA529_LVOL 0x03
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#define STA529_RVOL 0x04
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#define STA529_TTF0 0x05
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#define STA529_TTF1 0x06
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#define STA529_TTP0 0x07
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#define STA529_TTP1 0x08
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#define STA529_S2PCFG0 0x0A
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#define STA529_S2PCFG1 0x0B
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#define STA529_P2SCFG0 0x0C
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#define STA529_P2SCFG1 0x0D
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#define STA529_PLLCFG0 0x14
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#define STA529_PLLCFG1 0x15
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#define STA529_PLLCFG2 0x16
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#define STA529_PLLCFG3 0x17
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#define STA529_PLLPFE 0x18
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#define STA529_PLLST 0x19
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#define STA529_ADCCFG 0x1E /*mic_select*/
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#define STA529_CKOCFG 0x1F
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#define STA529_MISC 0x20
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#define STA529_PADST0 0x21
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#define STA529_PADST1 0x22
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#define STA529_FFXST 0x23
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#define STA529_PWMIN1 0x2D
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#define STA529_PWMIN2 0x2E
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#define STA529_POWST 0x32
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#define STA529_MAX_REGISTER 0x32
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#define STA529_RATES (SNDRV_PCM_RATE_8000 | \
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SNDRV_PCM_RATE_11025 | \
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SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_22050 | \
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SNDRV_PCM_RATE_32000 | \
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SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000)
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#define STA529_FORMAT (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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#define S2PC_VALUE 0x98
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#define CLOCK_OUT 0x60
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#define DATA_FORMAT_MSK 0x0E
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#define LEFT_J_DATA_FORMAT 0x00
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#define I2S_DATA_FORMAT 0x02
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#define RIGHT_J_DATA_FORMAT 0x04
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#define CODEC_MUTE_VAL 0x80
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#define POWER_CNTLMSAK 0x40
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#define POWER_STDBY 0x40
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#define FFX_MASK 0x80
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#define FFX_OFF 0x80
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#define POWER_UP 0x00
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#define FFX_CLK_ENB 0x01
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#define FFX_CLK_DIS 0x00
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#define FFX_CLK_MSK 0x01
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#define PLAY_FREQ_RANGE_MSK 0x70
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#define CAP_FREQ_RANGE_MSK 0x0C
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#define PDATA_LEN_MSK 0xC0
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#define BCLK_TO_FS_MSK 0x30
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#define AUDIO_MUTE_MSK 0x80
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static const struct reg_default sta529_reg_defaults[] = {
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{ 0, 0x35 }, /* R0 - FFX Configuration reg 0 */
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{ 1, 0xc8 }, /* R1 - FFX Configuration reg 1 */
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{ 2, 0x50 }, /* R2 - Master Volume */
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{ 3, 0x00 }, /* R3 - Left Volume */
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{ 4, 0x00 }, /* R4 - Right Volume */
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{ 10, 0xb2 }, /* R10 - S2P Config Reg 0 */
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{ 11, 0x41 }, /* R11 - S2P Config Reg 1 */
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{ 12, 0x92 }, /* R12 - P2S Config Reg 0 */
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{ 13, 0x41 }, /* R13 - P2S Config Reg 1 */
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{ 30, 0xd2 }, /* R30 - ADC Config Reg */
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{ 31, 0x40 }, /* R31 - clock Out Reg */
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{ 32, 0x21 }, /* R32 - Misc Register */
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};
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struct sta529 {
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struct regmap *regmap;
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};
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static bool sta529_readable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case STA529_FFXCFG0:
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case STA529_FFXCFG1:
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case STA529_MVOL:
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case STA529_LVOL:
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case STA529_RVOL:
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case STA529_S2PCFG0:
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case STA529_S2PCFG1:
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case STA529_P2SCFG0:
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case STA529_P2SCFG1:
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case STA529_ADCCFG:
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case STA529_CKOCFG:
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case STA529_MISC:
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return true;
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default:
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return false;
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}
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}
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static const char *pwm_mode_text[] = { "Binary", "Headphone", "Ternary",
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"Phase-shift"};
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static const DECLARE_TLV_DB_SCALE(out_gain_tlv, -9150, 50, 0);
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static const DECLARE_TLV_DB_SCALE(master_vol_tlv, -12750, 50, 0);
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static SOC_ENUM_SINGLE_DECL(pwm_src, STA529_FFXCFG1, 4, pwm_mode_text);
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static const struct snd_kcontrol_new sta529_snd_controls[] = {
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SOC_DOUBLE_R_TLV("Digital Playback Volume", STA529_LVOL, STA529_RVOL, 0,
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127, 0, out_gain_tlv),
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SOC_SINGLE_TLV("Master Playback Volume", STA529_MVOL, 0, 127, 1,
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master_vol_tlv),
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SOC_ENUM("PWM Select", pwm_src),
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};
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static int sta529_set_bias_level(struct snd_soc_component *component, enum
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snd_soc_bias_level level)
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{
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struct sta529 *sta529 = snd_soc_component_get_drvdata(component);
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switch (level) {
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case SND_SOC_BIAS_ON:
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case SND_SOC_BIAS_PREPARE:
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snd_soc_component_update_bits(component, STA529_FFXCFG0, POWER_CNTLMSAK,
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POWER_UP);
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snd_soc_component_update_bits(component, STA529_MISC, FFX_CLK_MSK,
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FFX_CLK_ENB);
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break;
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case SND_SOC_BIAS_STANDBY:
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if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
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regcache_sync(sta529->regmap);
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snd_soc_component_update_bits(component, STA529_FFXCFG0,
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POWER_CNTLMSAK, POWER_STDBY);
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/* Making FFX output to zero */
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snd_soc_component_update_bits(component, STA529_FFXCFG0, FFX_MASK,
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FFX_OFF);
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snd_soc_component_update_bits(component, STA529_MISC, FFX_CLK_MSK,
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FFX_CLK_DIS);
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break;
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case SND_SOC_BIAS_OFF:
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break;
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}
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return 0;
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}
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static int sta529_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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int pdata, play_freq_val, record_freq_val;
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int bclk_to_fs_ratio;
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switch (params_width(params)) {
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case 16:
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pdata = 1;
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bclk_to_fs_ratio = 0;
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break;
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case 24:
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pdata = 2;
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bclk_to_fs_ratio = 1;
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break;
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case 32:
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pdata = 3;
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bclk_to_fs_ratio = 2;
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break;
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default:
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dev_err(component->dev, "Unsupported format\n");
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return -EINVAL;
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}
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switch (params_rate(params)) {
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case 8000:
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case 11025:
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play_freq_val = 0;
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record_freq_val = 2;
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break;
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case 16000:
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case 22050:
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play_freq_val = 1;
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record_freq_val = 0;
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break;
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case 32000:
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case 44100:
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case 48000:
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play_freq_val = 2;
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record_freq_val = 0;
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break;
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default:
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dev_err(component->dev, "Unsupported rate\n");
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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snd_soc_component_update_bits(component, STA529_S2PCFG1, PDATA_LEN_MSK,
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pdata << 6);
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snd_soc_component_update_bits(component, STA529_S2PCFG1, BCLK_TO_FS_MSK,
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bclk_to_fs_ratio << 4);
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snd_soc_component_update_bits(component, STA529_MISC, PLAY_FREQ_RANGE_MSK,
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play_freq_val << 4);
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} else {
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snd_soc_component_update_bits(component, STA529_P2SCFG1, PDATA_LEN_MSK,
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pdata << 6);
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snd_soc_component_update_bits(component, STA529_P2SCFG1, BCLK_TO_FS_MSK,
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bclk_to_fs_ratio << 4);
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snd_soc_component_update_bits(component, STA529_MISC, CAP_FREQ_RANGE_MSK,
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record_freq_val << 2);
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}
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return 0;
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}
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static int sta529_mute(struct snd_soc_dai *dai, int mute, int direction)
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{
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u8 val = 0;
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if (mute)
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val |= CODEC_MUTE_VAL;
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snd_soc_component_update_bits(dai->component, STA529_FFXCFG0, AUDIO_MUTE_MSK, val);
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return 0;
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}
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static int sta529_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
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{
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struct snd_soc_component *component = codec_dai->component;
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u8 mode = 0;
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/* interface format */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_LEFT_J:
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mode = LEFT_J_DATA_FORMAT;
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break;
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case SND_SOC_DAIFMT_I2S:
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mode = I2S_DATA_FORMAT;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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mode = RIGHT_J_DATA_FORMAT;
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break;
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default:
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, STA529_S2PCFG0, DATA_FORMAT_MSK, mode);
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return 0;
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}
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static const struct snd_soc_dai_ops sta529_dai_ops = {
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.hw_params = sta529_hw_params,
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.set_fmt = sta529_set_dai_fmt,
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.mute_stream = sta529_mute,
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.no_capture_mute = 1,
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};
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static struct snd_soc_dai_driver sta529_dai = {
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.name = "sta529-audio",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = STA529_RATES,
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.formats = STA529_FORMAT,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = STA529_RATES,
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.formats = STA529_FORMAT,
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},
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.ops = &sta529_dai_ops,
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};
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static const struct snd_soc_component_driver sta529_component_driver = {
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.set_bias_level = sta529_set_bias_level,
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.controls = sta529_snd_controls,
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.num_controls = ARRAY_SIZE(sta529_snd_controls),
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.suspend_bias_off = 1,
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.idle_bias_on = 1,
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.use_pmdown_time = 1,
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.endianness = 1,
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};
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static const struct regmap_config sta529_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = STA529_MAX_REGISTER,
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.readable_reg = sta529_readable,
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.cache_type = REGCACHE_MAPLE,
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.reg_defaults = sta529_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(sta529_reg_defaults),
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};
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static int sta529_i2c_probe(struct i2c_client *i2c)
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{
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struct sta529 *sta529;
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int ret;
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sta529 = devm_kzalloc(&i2c->dev, sizeof(struct sta529), GFP_KERNEL);
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if (!sta529)
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return -ENOMEM;
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sta529->regmap = devm_regmap_init_i2c(i2c, &sta529_regmap);
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if (IS_ERR(sta529->regmap)) {
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ret = PTR_ERR(sta529->regmap);
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dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
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return ret;
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}
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i2c_set_clientdata(i2c, sta529);
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ret = devm_snd_soc_register_component(&i2c->dev,
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&sta529_component_driver, &sta529_dai, 1);
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if (ret != 0)
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dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
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return ret;
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}
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static const struct i2c_device_id sta529_i2c_id[] = {
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{ "sta529", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, sta529_i2c_id);
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static const struct of_device_id sta529_of_match[] = {
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{ .compatible = "st,sta529", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sta529_of_match);
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static struct i2c_driver sta529_i2c_driver = {
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.driver = {
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.name = "sta529",
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.of_match_table = sta529_of_match,
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},
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.probe = sta529_i2c_probe,
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.id_table = sta529_i2c_id,
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};
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module_i2c_driver(sta529_i2c_driver);
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MODULE_DESCRIPTION("ASoC STA529 codec driver");
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MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
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MODULE_LICENSE("GPL");
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