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f2635d45a7
Complete the missing and correct the TDM settings. Signed-off-by: Derek Fang <derek.fang@realtek.com> Link: https://lore.kernel.org/r/20221012030102.4042-1-derek.fang@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
165 lines
4.7 KiB
C
165 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* rt1019.h -- RT1019 ALSA SoC audio amplifier driver
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*
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* Copyright(c) 2021 Realtek Semiconductor Corp.
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*/
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#ifndef __RT1019_H__
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#define __RT1019_H__
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#define RT1019_DEVICE_ID_VAL 0x1019
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#define RT1019_DEVICE_ID_VAL2 0x6731
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#define RT1019_RESET 0x0000
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#define RT1019_IDS_CTRL 0x0011
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#define RT1019_ASEL_CTRL 0x0013
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#define RT1019_PWR_STRP_2 0x0019
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#define RT1019_BEEP_TONE 0x001b
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#define RT1019_VER_ID 0x005c
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#define RT1019_VEND_ID_1 0x005e
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#define RT1019_VEND_ID_2 0x005f
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#define RT1019_DEV_ID_1 0x0061
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#define RT1019_DEV_ID_2 0x0062
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#define RT1019_SDB_CTRL 0x0066
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#define RT1019_CLK_TREE_1 0x0100
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#define RT1019_CLK_TREE_2 0x0101
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#define RT1019_CLK_TREE_3 0x0102
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#define RT1019_PLL_1 0x0311
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#define RT1019_PLL_2 0x0312
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#define RT1019_PLL_3 0x0313
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#define RT1019_TDM_1 0x0400
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#define RT1019_TDM_2 0x0401
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#define RT1019_TDM_3 0x0402
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#define RT1019_DMIX_MONO_1 0x0504
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#define RT1019_DMIX_MONO_2 0x0505
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#define RT1019_BEEP_1 0x0b00
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#define RT1019_BEEP_2 0x0b01
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/* 0x0019 Power On Strap Control-2 */
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#define RT1019_AUTO_BITS_SEL_MASK (0x1 << 5)
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#define RT1019_AUTO_BITS_SEL_AUTO (0x1 << 5)
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#define RT1019_AUTO_BITS_SEL_MANU (0x0 << 5)
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#define RT1019_AUTO_CLK_SEL_MASK (0x1 << 4)
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#define RT1019_AUTO_CLK_SEL_AUTO (0x1 << 4)
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#define RT1019_AUTO_CLK_SEL_MANU (0x0 << 4)
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/* 0x0100 Clock Tree Control-1 */
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#define RT1019_CLK_SYS_PRE_SEL_MASK (0x1 << 7)
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#define RT1019_CLK_SYS_PRE_SEL_SFT 7
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#define RT1019_CLK_SYS_PRE_SEL_BCLK (0x0 << 7)
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#define RT1019_CLK_SYS_PRE_SEL_PLL (0x1 << 7)
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#define RT1019_PLL_SRC_MASK (0x1 << 4)
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#define RT1019_PLL_SRC_SFT 4
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#define RT1019_PLL_SRC_SEL_BCLK (0x0 << 4)
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#define RT1019_PLL_SRC_SEL_RC (0x1 << 4)
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#define RT1019_SEL_FIFO_MASK (0x3 << 2)
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#define RT1019_SEL_FIFO_DIV1 (0x0 << 2)
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#define RT1019_SEL_FIFO_DIV2 (0x1 << 2)
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#define RT1019_SEL_FIFO_DIV4 (0x2 << 2)
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/* 0x0101 clock tree control-2 */
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#define RT1019_SYS_DIV_DA_FIL_MASK (0x7 << 5)
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#define RT1019_SYS_DIV_DA_FIL_DIV1 (0x2 << 5)
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#define RT1019_SYS_DIV_DA_FIL_DIV2 (0x3 << 5)
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#define RT1019_SYS_DIV_DA_FIL_DIV4 (0x4 << 5)
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#define RT1019_SYS_DA_OSR_MASK (0x3 << 2)
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#define RT1019_SYS_DA_OSR_DIV1 (0x0 << 2)
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#define RT1019_SYS_DA_OSR_DIV2 (0x1 << 2)
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#define RT1019_SYS_DA_OSR_DIV4 (0x2 << 2)
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#define RT1019_ASRC_256FS_MASK 0x3
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#define RT1019_ASRC_256FS_DIV1 0x0
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#define RT1019_ASRC_256FS_DIV2 0x1
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#define RT1019_ASRC_256FS_DIV4 0x2
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/* 0x0102 clock tree control-3 */
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#define RT1019_SEL_CLK_CAL_MASK (0x3 << 6)
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#define RT1019_SEL_CLK_CAL_DIV1 (0x0 << 6)
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#define RT1019_SEL_CLK_CAL_DIV2 (0x1 << 6)
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#define RT1019_SEL_CLK_CAL_DIV4 (0x2 << 6)
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/* 0x0311 PLL-1 */
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#define RT1019_PLL_M_MASK (0xf << 4)
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#define RT1019_PLL_M_SFT 4
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#define RT1019_PLL_M_BP_MASK (0x1 << 1)
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#define RT1019_PLL_M_BP_SFT 1
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#define RT1019_PLL_Q_8_8_MASK (0x1)
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/* 0x0312 PLL-2 */
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#define RT1019_PLL_Q_7_0_MASK 0xff
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/* 0x0313 PLL-3 */
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#define RT1019_PLL_K_MASK 0x1f
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/* 0x0400 TDM Control-1 */
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#define RT1019_TDM_BCLK_MASK (0x1 << 6)
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#define RT1019_TDM_BCLK_NORM (0x0 << 6)
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#define RT1019_TDM_BCLK_INV (0x1 << 6)
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#define RT1019_TDM_CL_MASK (0x7)
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#define RT1019_TDM_CL_8 (0x4)
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#define RT1019_TDM_CL_32 (0x3)
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#define RT1019_TDM_CL_24 (0x2)
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#define RT1019_TDM_CL_20 (0x1)
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#define RT1019_TDM_CL_16 (0x0)
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/* 0x0401 TDM Control-2 */
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#define RT1019_I2S_CH_TX_MASK (0x3 << 6)
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#define RT1019_I2S_CH_TX_SFT 6
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#define RT1019_I2S_TX_2CH (0x0 << 6)
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#define RT1019_I2S_TX_4CH (0x1 << 6)
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#define RT1019_I2S_TX_6CH (0x2 << 6)
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#define RT1019_I2S_TX_8CH (0x3 << 6)
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#define RT1019_I2S_DF_MASK (0x7 << 3)
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#define RT1019_I2S_DF_SFT 3
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#define RT1019_I2S_DF_I2S (0x0 << 3)
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#define RT1019_I2S_DF_LEFT (0x1 << 3)
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#define RT1019_I2S_DF_PCM_A_R (0x2 << 3)
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#define RT1019_I2S_DF_PCM_B_R (0x3 << 3)
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#define RT1019_I2S_DF_PCM_A_F (0x6 << 3)
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#define RT1019_I2S_DF_PCM_B_F (0x7 << 3)
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#define RT1019_I2S_DL_MASK 0x7
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#define RT1019_I2S_DL_SFT 0
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#define RT1019_I2S_DL_16 0x0
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#define RT1019_I2S_DL_20 0x1
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#define RT1019_I2S_DL_24 0x2
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#define RT1019_I2S_DL_32 0x3
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#define RT1019_I2S_DL_8 0x4
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/* TDM1 Control-3 (0x0402) */
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#define RT1019_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 4)
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#define RT1019_TDM_I2S_TX_R_DAC1_1_MASK 0x7
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#define RT1019_TDM_I2S_TX_L_DAC1_1_SFT 4
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#define RT1019_TDM_I2S_TX_R_DAC1_1_SFT 0
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/* System Clock Source */
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enum {
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RT1019_SCLK_S_BCLK,
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RT1019_SCLK_S_PLL,
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};
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/* PLL1 Source */
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enum {
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RT1019_PLL_S_BCLK,
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RT1019_PLL_S_RC25M,
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};
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enum {
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RT1019_AIF1,
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RT1019_AIFS
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};
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struct rt1019_priv {
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struct snd_soc_component *component;
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struct regmap *regmap;
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int sysclk;
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int sysclk_src;
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int lrck;
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int bclk;
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int pll_src;
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int pll_in;
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int pll_out;
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unsigned int bclk_ratio;
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};
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#endif /* __RT1019_H__ */
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