Thomas Zimmermann 147696720e drm/mgag200: Select clock in PLL update functions ... Put the clock-selection code into each of the PLL-update functions to make them select the correct pixel clock. Instead of copying the code, introduce a new helper WREG_MISC_MASKED, which does masked writes into <MISC>. Use it from each individual PLL update function. The pixel clock for video output was not actually set before programming the clock's values. It worked because the device had the correct clock pre-set. v2: * don't duplicate <MISC> update code (Sam) Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: db05f8d3dc ("drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O") Acked-by: Sam Ravnborg <sam@ravnborg.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Emil Velikov <emil.velikov@collabora.com> Cc: Dave Airlie <airlied@redhat.com> Cc: dri-devel@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v5.9+ Link: https://patchwork.freedesktop.org/patch/msgid/20210714142240.21979-2-tzimmermann@suse.de		2021-08-08 20:13:10 +02:00
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drm	drm/mgag200: Select clock in PLL update functions	2021-08-08 20:13:10 +02:00
host1x	gpu: host1x: Split up client initalization and registration	2021-05-17 12:31:05 +02:00
ipu-v3	gpu: ipu-v3: Add Rec.709 limited range support to DP	2021-05-10 17:20:29 +02:00
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vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
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