mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-18 01:34:14 +08:00
145ff1ec09
- Removal of the tremendously unpopular read_barrier_depends() barrier, which is a NOP on all architectures apart from Alpha, in favour of allowing architectures to override READ_ONCE() and do whatever dance they need to do to ensure address dependencies provide LOAD -> LOAD/STORE ordering. This work also offers a potential solution if compilers are shown to convert LOAD -> LOAD address dependencies into control dependencies (e.g. under LTO), as weakly ordered architectures will effectively be able to upgrade READ_ONCE() to smp_load_acquire(). The latter case is not used yet, but will be discussed further at LPC. - Make the MSI/IOMMU input/output ID translation PCI agnostic, augment the MSI/IOMMU ACPI/OF ID mapping APIs to accept an input ID bus-specific parameter and apply the resulting changes to the device ID space provided by the Freescale FSL bus. - arm64 support for TLBI range operations and translation table level hints (part of the ARMv8.4 architecture version). - Time namespace support for arm64. - Export the virtual and physical address sizes in vmcoreinfo for makedumpfile and crash utilities. - CPU feature handling cleanups and checks for programmer errors (overlapping bit-fields). - ACPI updates for arm64: disallow AML accesses to EFI code regions and kernel memory. - perf updates for arm64. - Miscellaneous fixes and cleanups, most notably PLT counting optimisation for module loading, recordmcount fix to ignore relocations other than R_AARCH64_CALL26, CMA areas reserved for gigantic pages on 16K and 64K configurations. - Trivial typos, duplicate words. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAl8oTcsACgkQa9axLQDI XvEj6hAAkn39mO5xrR/Vhpg3DyFPk63ZlMSX9SsOeVyaLbovT6stTs1XAZXPpnkt rV3gwACyGSrqH6+uey9pHgHJuPF2TdrGEVK08yVKo9KGW/6yXSIncdKFE4jUJ/WJ wF5j7eMET2aGzcpm5AlzMmq6HOrKB8nZac9H8/x6H+Ox2WdgJkEjOkDvyqACUyum N3FsTZkWj2pIkTXHNgDZ8KjxVLO8HlFaB2hkxFDl9NPlX2UTCQJ8Tg1KiPLafKaK gUvH4usQDFdb5RU/UWogre37J4emO0ZTApZOyju+U+PMMWlWVHjZ4isUIS9zz/AE JNZ23dnKZX2HrYa5p8HZx175zwj/vXUqUHCZPLvQXaAudCEhF8BVljPiG0e80FV5 GHFUgUbylKspp01I/9L+2JvsG96Mr0e+P3Sx7L2HTI42cmtoSa14+MpoSRj7zlft Qcl8hfrVOjCjUnFRHa/1y1cGvnD9GbgnKJR7zgVxl9bD/Jd48r1HUtwRORZCzWFr mRPVbPS72fWxMzMV9DZYJm02jJY9kLX2BMl49njbB8MhAhzOvrMVzoVVtMMeRFLR XHeJpmg36W09FiRGe7LRXlkXIhCQzQG2bJfiphuupCfhjRAitPoq8I925G6Pig60 c8RWaXGU7PrEsdMNrL83vekvGKgqrkoFkRVtsCoQ2X6Hvu/XdYI= =mh79 -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 and cross-arch updates from Catalin Marinas: "Here's a slightly wider-spread set of updates for 5.9. Going outside the usual arch/arm64/ area is the removal of read_barrier_depends() series from Will and the MSI/IOMMU ID translation series from Lorenzo. The notable arm64 updates include ARMv8.4 TLBI range operations and translation level hint, time namespace support, and perf. Summary: - Removal of the tremendously unpopular read_barrier_depends() barrier, which is a NOP on all architectures apart from Alpha, in favour of allowing architectures to override READ_ONCE() and do whatever dance they need to do to ensure address dependencies provide LOAD -> LOAD/STORE ordering. This work also offers a potential solution if compilers are shown to convert LOAD -> LOAD address dependencies into control dependencies (e.g. under LTO), as weakly ordered architectures will effectively be able to upgrade READ_ONCE() to smp_load_acquire(). The latter case is not used yet, but will be discussed further at LPC. - Make the MSI/IOMMU input/output ID translation PCI agnostic, augment the MSI/IOMMU ACPI/OF ID mapping APIs to accept an input ID bus-specific parameter and apply the resulting changes to the device ID space provided by the Freescale FSL bus. - arm64 support for TLBI range operations and translation table level hints (part of the ARMv8.4 architecture version). - Time namespace support for arm64. - Export the virtual and physical address sizes in vmcoreinfo for makedumpfile and crash utilities. - CPU feature handling cleanups and checks for programmer errors (overlapping bit-fields). - ACPI updates for arm64: disallow AML accesses to EFI code regions and kernel memory. - perf updates for arm64. - Miscellaneous fixes and cleanups, most notably PLT counting optimisation for module loading, recordmcount fix to ignore relocations other than R_AARCH64_CALL26, CMA areas reserved for gigantic pages on 16K and 64K configurations. - Trivial typos, duplicate words" Link: http://lkml.kernel.org/r/20200710165203.31284-1-will@kernel.org Link: http://lkml.kernel.org/r/20200619082013.13661-1-lorenzo.pieralisi@arm.com * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (82 commits) arm64: use IRQ_STACK_SIZE instead of THREAD_SIZE for irq stack arm64/mm: save memory access in check_and_switch_context() fast switch path arm64: sigcontext.h: delete duplicated word arm64: ptrace.h: delete duplicated word arm64: pgtable-hwdef.h: delete duplicated words bus: fsl-mc: Add ACPI support for fsl-mc bus/fsl-mc: Refactor the MSI domain creation in the DPRC driver of/irq: Make of_msi_map_rid() PCI bus agnostic of/irq: make of_msi_map_get_device_domain() bus agnostic dt-bindings: arm: fsl: Add msi-map device-tree binding for fsl-mc bus of/device: Add input id to of_dma_configure() of/iommu: Make of_map_rid() PCI agnostic ACPI/IORT: Add an input ID to acpi_dma_configure() ACPI/IORT: Remove useless PCI bus walk ACPI/IORT: Make iort_msi_map_rid() PCI agnostic ACPI/IORT: Make iort_get_device_domain IRQ domain agnostic ACPI/IORT: Make iort_match_node_callback walk the ACPI namespace for NC arm64: enable time namespace support arm64/vdso: Restrict splitting VVAR VMA arm64/vdso: Handle faults on timens page ...
270 lines
5.9 KiB
ArmAsm
270 lines
5.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ld script to make ARM Linux kernel
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* taken from the i386 version by Russell King
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* Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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*/
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#define RO_EXCEPTION_TABLE_ALIGN 8
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/cache.h>
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#include <asm/kernel-pgtable.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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#include "image.h"
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OUTPUT_ARCH(aarch64)
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ENTRY(_text)
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jiffies = jiffies_64;
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#define HYPERVISOR_TEXT \
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/* \
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* Align to 4 KB so that \
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* a) the HYP vector table is at its minimum \
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* alignment of 2048 bytes \
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* b) the HYP init code will not cross a page \
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* boundary if its size does not exceed \
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* 4 KB (see related ASSERT() below) \
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*/ \
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. = ALIGN(SZ_4K); \
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__hyp_idmap_text_start = .; \
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*(.hyp.idmap.text) \
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__hyp_idmap_text_end = .; \
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__hyp_text_start = .; \
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*(.hyp.text) \
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__hyp_text_end = .;
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#define IDMAP_TEXT \
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. = ALIGN(SZ_4K); \
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__idmap_text_start = .; \
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*(.idmap.text) \
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__idmap_text_end = .;
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#ifdef CONFIG_HIBERNATION
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#define HIBERNATE_TEXT \
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. = ALIGN(SZ_4K); \
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__hibernate_exit_text_start = .; \
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*(.hibernate_exit.text) \
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__hibernate_exit_text_end = .;
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#else
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#define HIBERNATE_TEXT
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#endif
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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#define TRAMP_TEXT \
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. = ALIGN(PAGE_SIZE); \
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__entry_tramp_text_start = .; \
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*(.entry.tramp.text) \
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. = ALIGN(PAGE_SIZE); \
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__entry_tramp_text_end = .;
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#else
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#define TRAMP_TEXT
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#endif
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/*
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* The size of the PE/COFF section that covers the kernel image, which
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* runs from _stext to _edata, must be a round multiple of the PE/COFF
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* FileAlignment, which we set to its minimum value of 0x200. '_stext'
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* itself is 4 KB aligned, so padding out _edata to a 0x200 aligned
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* boundary should be sufficient.
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*/
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PECOFF_FILE_ALIGNMENT = 0x200;
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#ifdef CONFIG_EFI
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#define PECOFF_EDATA_PADDING \
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.pecoff_edata_padding : { BYTE(0); . = ALIGN(PECOFF_FILE_ALIGNMENT); }
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#else
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#define PECOFF_EDATA_PADDING
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#endif
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SECTIONS
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{
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/*
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* XXX: The linker does not define how output sections are
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* assigned to input sections when there are multiple statements
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* matching the same input section name. There is no documented
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* order of matching.
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*/
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/DISCARD/ : {
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EXIT_CALL
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*(.discard)
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*(.discard.*)
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*(.interp .dynamic)
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*(.dynsym .dynstr .hash .gnu.hash)
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*(.eh_frame)
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}
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. = KIMAGE_VADDR + TEXT_OFFSET;
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.head.text : {
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_text = .;
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HEAD_TEXT
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}
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.text : { /* Real text segment */
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_stext = .; /* Text and read-only data */
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IRQENTRY_TEXT
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SOFTIRQENTRY_TEXT
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ENTRY_TEXT
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TEXT_TEXT
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SCHED_TEXT
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CPUIDLE_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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HYPERVISOR_TEXT
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IDMAP_TEXT
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HIBERNATE_TEXT
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TRAMP_TEXT
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*(.fixup)
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*(.gnu.warning)
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. = ALIGN(16);
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*(.got) /* Global offset table */
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}
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. = ALIGN(SEGMENT_ALIGN);
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_etext = .; /* End of text section */
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/* everything from this point to __init_begin will be marked RO NX */
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RO_DATA(PAGE_SIZE)
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idmap_pg_dir = .;
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. += IDMAP_DIR_SIZE;
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idmap_pg_end = .;
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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tramp_pg_dir = .;
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. += PAGE_SIZE;
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#endif
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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reserved_ttbr0 = .;
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. += RESERVED_TTBR0_SIZE;
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#endif
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swapper_pg_dir = .;
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. += PAGE_SIZE;
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swapper_pg_end = .;
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. = ALIGN(SEGMENT_ALIGN);
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__init_begin = .;
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__inittext_begin = .;
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INIT_TEXT_SECTION(8)
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__exittext_begin = .;
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.exit.text : {
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EXIT_TEXT
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}
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__exittext_end = .;
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. = ALIGN(4);
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.altinstructions : {
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__alt_instructions = .;
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*(.altinstructions)
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__alt_instructions_end = .;
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}
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. = ALIGN(SEGMENT_ALIGN);
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__inittext_end = .;
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__initdata_begin = .;
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.init.data : {
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INIT_DATA
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INIT_SETUP(16)
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INIT_CALLS
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CON_INITCALL
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INIT_RAM_FS
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*(.init.rodata.* .init.bss) /* from the EFI stub */
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}
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.exit.data : {
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EXIT_DATA
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}
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PERCPU_SECTION(L1_CACHE_BYTES)
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.rela.dyn : ALIGN(8) {
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*(.rela .rela*)
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}
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__rela_offset = ABSOLUTE(ADDR(.rela.dyn) - KIMAGE_VADDR);
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__rela_size = SIZEOF(.rela.dyn);
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#ifdef CONFIG_RELR
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.relr.dyn : ALIGN(8) {
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*(.relr.dyn)
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}
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__relr_offset = ABSOLUTE(ADDR(.relr.dyn) - KIMAGE_VADDR);
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__relr_size = SIZEOF(.relr.dyn);
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#endif
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. = ALIGN(SEGMENT_ALIGN);
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__initdata_end = .;
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__init_end = .;
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_data = .;
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_sdata = .;
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RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_ALIGN)
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/*
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* Data written with the MMU off but read with the MMU on requires
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* cache lines to be invalidated, discarding up to a Cache Writeback
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* Granule (CWG) of data from the cache. Keep the section that
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* requires this type of maintenance to be in its own Cache Writeback
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* Granule (CWG) area so the cache maintenance operations don't
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* interfere with adjacent data.
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*/
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.mmuoff.data.write : ALIGN(SZ_2K) {
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__mmuoff_data_start = .;
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*(.mmuoff.data.write)
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}
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. = ALIGN(SZ_2K);
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.mmuoff.data.read : {
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*(.mmuoff.data.read)
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__mmuoff_data_end = .;
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}
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PECOFF_EDATA_PADDING
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__pecoff_data_rawsize = ABSOLUTE(. - __initdata_begin);
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_edata = .;
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BSS_SECTION(0, 0, 0)
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. = ALIGN(PAGE_SIZE);
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init_pg_dir = .;
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. += INIT_DIR_SIZE;
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init_pg_end = .;
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. = ALIGN(SEGMENT_ALIGN);
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__pecoff_data_size = ABSOLUTE(. - __initdata_begin);
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_end = .;
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STABS_DEBUG
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HEAD_SYMBOLS
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}
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#include "image-vars.h"
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/*
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* The HYP init code and ID map text can't be longer than a page each,
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* and should not cross a page boundary.
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*/
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ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & ~(SZ_4K - 1)) <= SZ_4K,
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"HYP init code too big or misaligned")
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ASSERT(__idmap_text_end - (__idmap_text_start & ~(SZ_4K - 1)) <= SZ_4K,
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"ID map text too big or misaligned")
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#ifdef CONFIG_HIBERNATION
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ASSERT(__hibernate_exit_text_end - (__hibernate_exit_text_start & ~(SZ_4K - 1))
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<= SZ_4K, "Hibernate exit text too big or misaligned")
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#endif
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) == PAGE_SIZE,
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"Entry trampoline text too big")
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#endif
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/*
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* If padding is applied before .head.text, virt<->phys conversions will fail.
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*/
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ASSERT(_text == (KIMAGE_VADDR + TEXT_OFFSET), "HEAD is misaligned")
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