Srinivas Pandruvada 1434a3d357 tools/power/x86/intel-speed-select: Display TRL buckets for just base config level ... When only base config level is present, this tool is displaying TRL (Turbo-ratio-limits) by reading legacy MSR. In this case, also present core count for TRL by reading MSR 0x1AE. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>		2019-11-21 14:31:34 +02:00
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.gitignore	tools/power/x86/intel-speed-select: Add .gitignore file	2019-07-12 16:00:38 +03:00
Build
isst-config.c	tools/power/x86/intel-speed-select: Increment version	2019-11-07 19:00:25 +02:00
isst-core.c	tools/power/x86/intel-speed-select: Display TRL buckets for just base config level	2019-11-21 14:31:34 +02:00
isst-display.c	tools/power/x86/intel-speed-select: Ignore missing config level	2019-11-21 14:27:32 +02:00
isst.h	tools/power/x86/intel-speed-select: Use core count for base-freq mask	2019-11-07 19:00:25 +02:00
Makefile