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493 lines
15 KiB
Plaintext
493 lines
15 KiB
Plaintext
# Put here option for CPU selection and depending optimization
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if !X86_ELAN
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choice
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prompt "Processor family"
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default M686 if X86_32
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default GENERIC_CPU if X86_64
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config M386
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bool "386"
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depends on X86_32 && !UML
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---help---
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This is the processor type of your CPU. This information is used for
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optimizing purposes. In order to compile a kernel that can run on
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all x86 CPU types (albeit not optimally fast), you can specify
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"386" here.
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The kernel will not necessarily run on earlier architectures than
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the one you have chosen, e.g. a Pentium optimized kernel will run on
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a PPro, but not necessarily on a i486.
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Here are the settings recommended for greatest speed:
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- "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
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486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386
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class machine.
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- "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
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SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
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- "586" for generic Pentium CPUs lacking the TSC
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(time stamp counter) register.
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- "Pentium-Classic" for the Intel Pentium.
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- "Pentium-MMX" for the Intel Pentium MMX.
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- "Pentium-Pro" for the Intel Pentium Pro.
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- "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
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- "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
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- "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
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- "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
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- "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
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- "Crusoe" for the Transmeta Crusoe series.
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- "Efficeon" for the Transmeta Efficeon series.
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- "Winchip-C6" for original IDT Winchip.
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- "Winchip-2" for IDT Winchip 2.
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- "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
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- "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
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- "Geode GX/LX" For AMD Geode GX and LX processors.
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- "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
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- "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
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- "VIA C7" for VIA C7.
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If you don't know what to do, choose "386".
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config M486
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bool "486"
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depends on X86_32
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help
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Select this for a 486 series processor, either Intel or one of the
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compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
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DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
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U5S.
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config M586
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bool "586/K5/5x86/6x86/6x86MX"
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depends on X86_32
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help
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Select this for an 586 or 686 series processor such as the AMD K5,
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the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
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assume the RDTSC (Read Time Stamp Counter) instruction.
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config M586TSC
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bool "Pentium-Classic"
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depends on X86_32
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help
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Select this for a Pentium Classic processor with the RDTSC (Read
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Time Stamp Counter) instruction for benchmarking.
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config M586MMX
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bool "Pentium-MMX"
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depends on X86_32
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help
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Select this for a Pentium with the MMX graphics/multimedia
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extended instructions.
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config M686
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bool "Pentium-Pro"
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depends on X86_32
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help
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Select this for Intel Pentium Pro chips. This enables the use of
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Pentium Pro extended instructions, and disables the init-time guard
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against the f00f bug found in earlier Pentiums.
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config MPENTIUMII
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bool "Pentium-II/Celeron(pre-Coppermine)"
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depends on X86_32
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help
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Select this for Intel chips based on the Pentium-II and
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pre-Coppermine Celeron core. This option enables an unaligned
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copy optimization, compiles the kernel with optimization flags
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tailored for the chip, and applies any applicable Pentium Pro
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optimizations.
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config MPENTIUMIII
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bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
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depends on X86_32
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help
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Select this for Intel chips based on the Pentium-III and
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Celeron-Coppermine core. This option enables use of some
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extended prefetch instructions in addition to the Pentium II
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extensions.
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config MPENTIUMM
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bool "Pentium M"
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depends on X86_32
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help
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Select this for Intel Pentium M (not Pentium-4 M)
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notebook chips.
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config MPENTIUM4
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bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
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depends on X86_32
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help
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Select this for Intel Pentium 4 chips. This includes the
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Pentium 4, Pentium D, P4-based Celeron and Xeon, and
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Pentium-4 M (not Pentium M) chips. This option enables compile
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flags optimized for the chip, uses the correct cache line size, and
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applies any applicable optimizations.
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CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
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Select this for:
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Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
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-Willamette
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-Northwood
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-Mobile Pentium 4
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-Mobile Pentium 4 M
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-Extreme Edition (Gallatin)
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-Prescott
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-Prescott 2M
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-Cedar Mill
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-Presler
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-Smithfiled
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Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
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-Foster
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-Prestonia
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-Gallatin
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-Nocona
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-Irwindale
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-Cranford
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-Potomac
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-Paxville
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-Dempsey
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config MK6
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bool "K6/K6-II/K6-III"
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depends on X86_32
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help
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Select this for an AMD K6-family processor. Enables use of
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some extended instructions, and passes appropriate optimization
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flags to GCC.
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config MK7
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bool "Athlon/Duron/K7"
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depends on X86_32
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help
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Select this for an AMD Athlon K7-family processor. Enables use of
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some extended instructions, and passes appropriate optimization
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flags to GCC.
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config MK8
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bool "Opteron/Athlon64/Hammer/K8"
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help
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Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables
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use of some extended instructions, and passes appropriate optimization
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flags to GCC.
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config MCRUSOE
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bool "Crusoe"
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depends on X86_32
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help
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Select this for a Transmeta Crusoe processor. Treats the processor
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like a 586 with TSC, and sets some GCC optimization flags (like a
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Pentium Pro with no alignment requirements).
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config MEFFICEON
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bool "Efficeon"
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depends on X86_32
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help
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Select this for a Transmeta Efficeon processor.
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config MWINCHIPC6
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bool "Winchip-C6"
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depends on X86_32
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help
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Select this for an IDT Winchip C6 chip. Linux and GCC
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treat this chip as a 586TSC with some extended instructions
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and alignment requirements.
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config MWINCHIP2
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bool "Winchip-2"
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depends on X86_32
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help
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Select this for an IDT Winchip-2. Linux and GCC
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treat this chip as a 586TSC with some extended instructions
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and alignment requirements.
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config MWINCHIP3D
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bool "Winchip-2A/Winchip-3"
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depends on X86_32
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help
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Select this for an IDT Winchip-2A or 3. Linux and GCC
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treat this chip as a 586TSC with some extended instructions
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and alignment requirements. Also enable out of order memory
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stores for this CPU, which can increase performance of some
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operations.
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config MGEODEGX1
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bool "GeodeGX1"
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depends on X86_32
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help
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Select this for a Geode GX1 (Cyrix MediaGX) chip.
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config MGEODE_LX
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bool "Geode GX/LX"
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depends on X86_32
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help
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Select this for AMD Geode GX and LX processors.
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config MCYRIXIII
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bool "CyrixIII/VIA-C3"
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depends on X86_32
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help
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Select this for a Cyrix III or C3 chip. Presently Linux and GCC
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treat this chip as a generic 586. Whilst the CPU is 686 class,
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it lacks the cmov extension which gcc assumes is present when
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generating 686 code.
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Note that Nehemiah (Model 9) and above will not boot with this
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kernel due to them lacking the 3DNow! instructions used in earlier
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incarnations of the CPU.
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config MVIAC3_2
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bool "VIA C3-2 (Nehemiah)"
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depends on X86_32
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help
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Select this for a VIA C3 "Nehemiah". Selecting this enables usage
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of SSE and tells gcc to treat the CPU as a 686.
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Note, this kernel will not boot on older (pre model 9) C3s.
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config MVIAC7
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bool "VIA C7"
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depends on X86_32
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help
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Select this for a VIA C7. Selecting this uses the correct cache
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shift and tells gcc to treat the CPU as a 686.
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config MPSC
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bool "Intel P4 / older Netburst based Xeon"
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depends on X86_64
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help
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Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
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Xeon CPUs with Intel 64bit which is compatible with x86-64.
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Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
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Netburst core and shouldn't use this option. You can distinguish them
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using the cpu family field
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in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
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config MCORE2
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bool "Core 2/newer Xeon"
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help
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Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx)
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CPUs. You can distinguish newer from older Xeons by the CPU family
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in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo)
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config GENERIC_CPU
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bool "Generic-x86-64"
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depends on X86_64
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help
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Generic x86-64 CPU.
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Run equally well on all x86-64 CPUs.
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endchoice
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config X86_GENERIC
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bool "Generic x86 support"
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depends on X86_32
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help
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Instead of just including optimizations for the selected
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x86 variant (e.g. PII, Crusoe or Athlon), include some more
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generic optimizations as well. This will make the kernel
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perform better on x86 CPUs other than that selected.
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This is really intended for distributors who need more
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generic optimizations.
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endif
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config X86_CPU
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def_bool y
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select GENERIC_FIND_FIRST_BIT
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select GENERIC_FIND_NEXT_BIT
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#
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# Define implied options from the CPU selection here
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config X86_L1_CACHE_BYTES
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int
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default "128" if GENERIC_CPU || MPSC
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default "64" if MK8 || MCORE2
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depends on X86_64
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config X86_INTERNODE_CACHE_BYTES
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int
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default "4096" if X86_VSMP
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default X86_L1_CACHE_BYTES if !X86_VSMP
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depends on X86_64
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config X86_CMPXCHG
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def_bool X86_64 || (X86_32 && !M386)
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config X86_L1_CACHE_SHIFT
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int
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default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC
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default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
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default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
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default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7
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config X86_XADD
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def_bool y
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depends on X86_32 && !M386
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config X86_PPRO_FENCE
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bool "PentiumPro memory ordering errata workaround"
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depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
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help
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Old PentiumPro multiprocessor systems had errata that could cause memory
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operations to violate the x86 ordering standard in rare cases. Enabling this
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option will attempt to work around some (but not all) occurances of
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this problem, at the cost of much heavier spinlock and memory barrier
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operations.
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If unsure, say n here. Even distro kernels should think twice before enabling
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this: there are few systems, and an unlikely bug.
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config X86_F00F_BUG
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def_bool y
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depends on M586MMX || M586TSC || M586 || M486 || M386
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config X86_WP_WORKS_OK
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def_bool y
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depends on !M386
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config X86_INVLPG
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def_bool y
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depends on X86_32 && !M386
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config X86_BSWAP
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def_bool y
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depends on X86_32 && !M386
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config X86_POPAD_OK
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def_bool y
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depends on X86_32 && !M386
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config X86_ALIGNMENT_16
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def_bool y
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depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
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config X86_INTEL_USERCOPY
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def_bool y
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depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
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config X86_USE_PPRO_CHECKSUM
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def_bool y
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depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2
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config X86_USE_3DNOW
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def_bool y
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depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
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config X86_OOSTORE
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def_bool y
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depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR
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#
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# P6_NOPs are a relatively minor optimization that require a family >=
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# 6 processor, except that it is broken on certain VIA chips.
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# Furthermore, AMD chips prefer a totally different sequence of NOPs
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# (which work on all CPUs). In addition, it looks like Virtual PC
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# does not understand them.
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#
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# As a result, disallow these if we're not compiling for X86_64 (these
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# NOPs do work on all x86-64 capable chips); the list of processors in
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# the right-hand clause are the cores that benefit from this optimization.
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#
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config X86_P6_NOP
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def_bool y
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depends on X86_64
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depends on (MCORE2 || MPENTIUM4 || MPSC)
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config X86_TSC
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def_bool y
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depends on ((MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
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config X86_CMPXCHG64
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def_bool y
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depends on X86_PAE || X86_64
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# this should be set for all -march=.. options where the compiler
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# generates cmov.
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config X86_CMOV
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def_bool y
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depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || X86_64)
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config X86_MINIMUM_CPU_FAMILY
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int
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default "64" if X86_64
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default "6" if X86_32 && X86_P6_NOP
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default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
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default "3"
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config X86_DEBUGCTLMSR
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def_bool y
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depends on !(MK6 || MWINCHIPC6 || MWINCHIP2 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386)
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menuconfig PROCESSOR_SELECT
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default y
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bool "Supported processor vendors" if EMBEDDED
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help
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This lets you choose what x86 vendor support code your kernel
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will include.
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config CPU_SUP_INTEL
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default y
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bool "Support Intel processors" if PROCESSOR_SELECT
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help
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This enables extended support for Intel processors
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config CPU_SUP_CYRIX_32
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default y
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bool "Support Cyrix processors" if PROCESSOR_SELECT
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depends on !64BIT
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help
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This enables extended support for Cyrix processors
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config CPU_SUP_AMD
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default y
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bool "Support AMD processors" if PROCESSOR_SELECT
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help
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This enables extended support for AMD processors
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config CPU_SUP_CENTAUR_32
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default y
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bool "Support Centaur processors" if PROCESSOR_SELECT
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depends on !64BIT
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help
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This enables extended support for Centaur processors
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config CPU_SUP_CENTAUR_64
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default y
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bool "Support Centaur processors" if PROCESSOR_SELECT
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depends on 64BIT
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help
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This enables extended support for Centaur processors
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config CPU_SUP_TRANSMETA_32
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default y
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bool "Support Transmeta processors" if PROCESSOR_SELECT
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depends on !64BIT
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help
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This enables extended support for Transmeta processors
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config CPU_SUP_UMC_32
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default y
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bool "Support UMC processors" if PROCESSOR_SELECT
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depends on !64BIT
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help
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This enables extended support for UMC processors
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config X86_DS
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bool "Debug Store support"
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default y
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help
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Add support for Debug Store.
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This allows the kernel to provide a memory buffer to the hardware
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to store various profiling and tracing events.
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config X86_PTRACE_BTS
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bool "ptrace interface to Branch Trace Store"
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default y
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depends on (X86_DS && X86_DEBUGCTLMSR)
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help
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Add a ptrace interface to allow collecting an execution trace
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of the traced task.
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This collects control flow changes in a (cyclic) buffer and allows
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debuggers to fill in the gaps and show an execution trace of the debuggee.
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