mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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88a99886c2
cycle
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing
all call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a
combined call to irq_set_chained_handler_and_data(). This
series was created by Thomas Gleixner after the problem was
observed by Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which
is way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs
from IRQ numbers. The goal is to get rid of the irq number
from the handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw
spinlocks in IRQ handlers to play nice with the realtime
patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner
sun4i driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC
subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.
Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.
[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
815 lines
18 KiB
Plaintext
815 lines
18 KiB
Plaintext
/*
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* Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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reg = <0x00000000 0x04000000>,
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<0x08000000 0x04000000>;
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};
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L2: l2-cache {
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compatible = "arm,l210-cache";
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reg = <0x10210000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <30>;
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cache-unified;
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cache-level = <2>;
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cache-size = <131072>;
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cache-sets = <512>;
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cache-line-size = <32>;
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/* At full speed latency must be >=2 */
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arm,tag-latency = <2>;
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arm,data-latency = <2 2>;
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arm,dirty-latency = <2>;
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};
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mtu0: mtu@101e2000 {
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/* Nomadik system timer */
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compatible = "st,nomadik-mtu";
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reg = <0x101e2000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <4>;
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clocks = <&timclk>, <&pclk>;
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clock-names = "timclk", "apb_pclk";
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};
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mtu1: mtu@101e3000 {
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/* Secondary timer */
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reg = <0x101e3000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <5>;
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clocks = <&timclk>, <&pclk>;
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clock-names = "timclk", "apb_pclk";
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};
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gpio0: gpio@101e4000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e4000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <6>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <0>;
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gpio-ranges = <&pinctrl 0 0 32>;
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clocks = <&pclk>;
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};
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gpio1: gpio@101e5000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e5000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <1>;
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gpio-ranges = <&pinctrl 0 32 32>;
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clocks = <&pclk>;
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};
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gpio2: gpio@101e6000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e6000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <2>;
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gpio-ranges = <&pinctrl 0 64 32>;
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clocks = <&pclk>;
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};
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gpio3: gpio@101e7000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e7000 0x80>;
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ngpio = <28>;
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interrupt-parent = <&vica>;
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interrupts = <9>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <3>;
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gpio-ranges = <&pinctrl 0 96 28>;
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clocks = <&pclk>;
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};
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pinctrl: pinctrl {
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compatible = "stericsson,stn8815-pinctrl";
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nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
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/* Pin configurations */
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uart1 {
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uart1_default_mux: uart1_mux {
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u1_default_mux {
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function = "u1";
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groups = "u1_a_1";
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};
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};
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};
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mmcsd {
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mmcsd_default_mux: mmcsd_mux {
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mmcsd_default_mux {
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function = "mmcsd";
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groups = "mmcsd_a_1", "mmcsd_b_1";
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};
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};
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mmcsd_default_mode: mmcsd_default {
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mmcsd_default_cfg1 {
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/* MCCLK */
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pins = "GPIO8_B10";
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ste,output = <0>;
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};
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mmcsd_default_cfg2 {
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/* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
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pins = "GPIO10_C11", "GPIO15_A12",
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"GPIO16_C13", "GPIO23_D15";
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ste,output = <1>;
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};
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mmcsd_default_cfg3 {
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/* MCCMD, MCDAT3-0, MCMSFBCLK */
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pins = "GPIO9_A10", "GPIO11_B11",
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"GPIO12_A11", "GPIO13_C12",
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"GPIO14_B12", "GPIO24_C15";
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ste,input = <1>;
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};
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};
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};
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i2c0 {
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i2c0_default_mux: i2c0_mux {
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i2c0_default_mux {
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function = "i2c0";
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groups = "i2c0_a_1";
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};
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};
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i2c0_default_mode: i2c0_default {
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i2c0_default_cfg {
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pins = "GPIO62_D3", "GPIO63_D2";
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ste,input = <0>;
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};
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};
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};
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i2c1 {
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i2c1_default_mux: i2c1_mux {
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i2c1_default_mux {
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function = "i2c1";
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groups = "i2c1_a_1";
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};
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};
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i2c1_default_mode: i2c1_default {
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i2c1_default_cfg {
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pins = "GPIO53_L4", "GPIO54_L3";
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ste,input = <0>;
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};
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};
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};
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};
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src: src@101e0000 {
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compatible = "stericsson,nomadik-src";
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reg = <0x101e0000 0x1000>;
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/*
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* MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
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* that is parent of TIMCLK, PLL1 and PLL2
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*/
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mxtal: mxtal@19.2M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* divided by 8. This clock is used by the timers and
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* watchdog. See page 105 ff.
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*/
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&mxtal>;
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};
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/* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
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pll1: pll1@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <1>;
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clocks = <&mxtal>;
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};
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/* HCLK divides the PLL1 with 1,2,3 or 4 */
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hclk: hclk@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-hclk-clock";
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clocks = <&pll1>;
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};
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/* The PCLK domain uses HCLK right off */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&hclk>;
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};
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/* PLL2 is usually 864 MHz and divided into a few fixed rates */
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pll2: pll2@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <2>;
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clocks = <&mxtal>;
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};
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clk216: clk216@216M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk108: clk108@108M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&clk216>;
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};
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clk72: clk72@72M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <12>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk48: clk48@48M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <18>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk27: clk27@27M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&clk108>;
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};
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/* This apparently exists as well */
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ulpiclk: ulpiclk@60M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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/*
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* IP AMBA bus clocks, driving the bus side of the
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* peripheral clocking, clock gates.
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*/
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hclkdma0: hclkdma0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <0>;
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clocks = <&hclk>;
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};
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hclksmc: hclksmc@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <1>;
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clocks = <&hclk>;
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};
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hclksdram: hclksdram@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <2>;
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clocks = <&hclk>;
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};
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hclkdma1: hclkdma1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <3>;
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clocks = <&hclk>;
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};
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hclkclcd: hclkclcd@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <4>;
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clocks = <&hclk>;
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};
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pclkirda: pclkirda@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <5>;
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clocks = <&pclk>;
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};
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pclkssp: pclkssp@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <6>;
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clocks = <&pclk>;
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};
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pclkuart0: pclkuart0@48M {
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#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <7>;
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|
clocks = <&pclk>;
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};
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pclksdi: pclksdi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <8>;
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clocks = <&pclk>;
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};
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pclki2c0: pclki2c0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <9>;
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clocks = <&pclk>;
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};
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pclki2c1: pclki2c1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <10>;
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clocks = <&pclk>;
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};
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pclkuart1: pclkuart1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <11>;
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clocks = <&pclk>;
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};
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pclkmsp0: pclkmsp0@48M {
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#clock-cells = <0>;
|
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compatible = "st,nomadik-src-clock";
|
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clock-id = <12>;
|
|
clocks = <&pclk>;
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};
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hclkusb: hclkusb@48M {
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|
#clock-cells = <0>;
|
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compatible = "st,nomadik-src-clock";
|
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clock-id = <13>;
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clocks = <&hclk>;
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};
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hclkdif: hclkdif@48M {
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#clock-cells = <0>;
|
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compatible = "st,nomadik-src-clock";
|
|
clock-id = <14>;
|
|
clocks = <&hclk>;
|
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};
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|
hclksaa: hclksaa@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <15>;
|
|
clocks = <&hclk>;
|
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};
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hclksva: hclksva@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <16>;
|
|
clocks = <&hclk>;
|
|
};
|
|
pclkhsi: pclkhsi@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <17>;
|
|
clocks = <&pclk>;
|
|
};
|
|
pclkxti: pclkxti@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <18>;
|
|
clocks = <&pclk>;
|
|
};
|
|
pclkuart2: pclkuart2@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <19>;
|
|
clocks = <&pclk>;
|
|
};
|
|
pclkmsp1: pclkmsp1@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <20>;
|
|
clocks = <&pclk>;
|
|
};
|
|
pclkmsp2: pclkmsp2@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <21>;
|
|
clocks = <&pclk>;
|
|
};
|
|
pclkowm: pclkowm@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <22>;
|
|
clocks = <&pclk>;
|
|
};
|
|
hclkhpi: hclkhpi@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <23>;
|
|
clocks = <&hclk>;
|
|
};
|
|
pclkske: pclkske@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <24>;
|
|
clocks = <&pclk>;
|
|
};
|
|
pclkhsem: pclkhsem@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <25>;
|
|
clocks = <&pclk>;
|
|
};
|
|
hclk3d: hclk3d@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <26>;
|
|
clocks = <&hclk>;
|
|
};
|
|
hclkhash: hclkhash@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <27>;
|
|
clocks = <&hclk>;
|
|
};
|
|
hclkcryp: hclkcryp@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <28>;
|
|
clocks = <&hclk>;
|
|
};
|
|
pclkmshc: pclkmshc@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <29>;
|
|
clocks = <&pclk>;
|
|
};
|
|
hclkusbm: hclkusbm@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <30>;
|
|
clocks = <&hclk>;
|
|
};
|
|
hclkrng: hclkrng@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <31>;
|
|
clocks = <&hclk>;
|
|
};
|
|
|
|
/* IP kernel clocks */
|
|
clcdclk: clcdclk@0 {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <36>;
|
|
clocks = <&clk72 &clk48>;
|
|
};
|
|
irdaclk: irdaclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <37>;
|
|
clocks = <&clk48>;
|
|
};
|
|
sspiclk: sspiclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <38>;
|
|
clocks = <&clk48>;
|
|
};
|
|
uart0clk: uart0clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <39>;
|
|
clocks = <&clk48>;
|
|
};
|
|
sdiclk: sdiclk@48M {
|
|
/* Also called MCCLK in some documents */
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <40>;
|
|
clocks = <&clk48>;
|
|
};
|
|
i2c0clk: i2c0clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <41>;
|
|
clocks = <&clk48>;
|
|
};
|
|
i2c1clk: i2c1clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <42>;
|
|
clocks = <&clk48>;
|
|
};
|
|
uart1clk: uart1clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <43>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mspclk0: mspclk0@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <44>;
|
|
clocks = <&clk48>;
|
|
};
|
|
usbclk: usbclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <45>;
|
|
clocks = <&clk48>; /* 48 MHz not ULPI */
|
|
};
|
|
difclk: difclk@72M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <46>;
|
|
clocks = <&clk72>;
|
|
};
|
|
ipi2cclk: ipi2cclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <47>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
ipbmcclk: ipbmcclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <48>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
hsiclkrx: hsiclkrx@216M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <49>;
|
|
clocks = <&clk216>;
|
|
};
|
|
hsiclktx: hsiclktx@108M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <50>;
|
|
clocks = <&clk108>;
|
|
};
|
|
uart2clk: uart2clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <51>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mspclk1: mspclk1@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <52>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mspclk2: mspclk2@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <53>;
|
|
clocks = <&clk48>;
|
|
};
|
|
owmclk: owmclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <54>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
skeclk: skeclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <56>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
x3dclk: x3dclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <58>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
pclkmsp3: pclkmsp3@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <59>;
|
|
clocks = <&pclk>;
|
|
};
|
|
mspclk3: mspclk3@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <60>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mshcclk: mshcclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <61>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
usbmclk: usbmclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <62>;
|
|
/* Stated as "48 MHz not ULPI clock" */
|
|
clocks = <&clk48>;
|
|
};
|
|
rngcclk: rngcclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <63>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
};
|
|
|
|
/* A NAND flash of 128 MiB */
|
|
fsmc: flash@40000000 {
|
|
compatible = "stericsson,fsmc-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x10100000 0x1000>, /* FSMC Register*/
|
|
<0x40000000 0x2000>, /* NAND Base DATA */
|
|
<0x41000000 0x2000>, /* NAND Base ADDR */
|
|
<0x40800000 0x2000>; /* NAND Base CMD */
|
|
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
|
|
clocks = <&hclksmc>;
|
|
status = "okay";
|
|
timings = /bits/ 8 <0 0 0 0x10 0x0a 0>;
|
|
|
|
partition@0 {
|
|
label = "X-Loader(NAND)";
|
|
reg = <0x0 0x40000>;
|
|
};
|
|
partition@40000 {
|
|
label = "MemInit(NAND)";
|
|
reg = <0x40000 0x40000>;
|
|
};
|
|
partition@80000 {
|
|
label = "BootLoader(NAND)";
|
|
reg = <0x80000 0x200000>;
|
|
};
|
|
partition@280000 {
|
|
label = "Kernel zImage(NAND)";
|
|
reg = <0x280000 0x300000>;
|
|
};
|
|
partition@580000 {
|
|
label = "Root Filesystem(NAND)";
|
|
reg = <0x580000 0x1600000>;
|
|
};
|
|
partition@1b80000 {
|
|
label = "User Filesystem(NAND)";
|
|
reg = <0x1b80000 0x6480000>;
|
|
};
|
|
};
|
|
|
|
/* I2C0 connected to the STw4811 power management chip */
|
|
i2c0 {
|
|
compatible = "st,nomadik-i2c", "arm,primecell";
|
|
reg = <0x101f8000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <20>;
|
|
clock-frequency = <100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&i2c0clk>, <&pclki2c0>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
|
|
|
|
stw4811@2d {
|
|
compatible = "st,stw4811";
|
|
reg = <0x2d>;
|
|
vmmc_regulator: vmmc {
|
|
compatible = "st,stw481x-vmmc";
|
|
regulator-name = "VMMC";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* I2C1 connected to various sensors */
|
|
i2c1 {
|
|
compatible = "st,nomadik-i2c", "arm,primecell";
|
|
reg = <0x101f7000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <21>;
|
|
clock-frequency = <100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&i2c1clk>, <&pclki2c1>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
|
|
|
|
camera@2d {
|
|
compatible = "st,camera";
|
|
reg = <0x10>;
|
|
};
|
|
stw5095@1a {
|
|
compatible = "st,stw5095";
|
|
reg = <0x1a>;
|
|
};
|
|
};
|
|
|
|
amba {
|
|
compatible = "arm,amba-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
vica: intc@10140000 {
|
|
compatible = "arm,versatile-vic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x10140000 0x20>;
|
|
};
|
|
|
|
vicb: intc@10140020 {
|
|
compatible = "arm,versatile-vic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x10140020 0x20>;
|
|
};
|
|
|
|
uart0: uart@101fd000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x101fd000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <12>;
|
|
clocks = <&uart0clk>, <&pclkuart0>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: uart@101fb000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x101fb000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <17>;
|
|
clocks = <&uart1clk>, <&pclkuart1>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_default_mux>;
|
|
};
|
|
|
|
uart2: uart@101f2000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x101f2000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <28>;
|
|
clocks = <&uart2clk>, <&pclkuart2>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@101b0000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x101b0000 0x1000>;
|
|
clocks = <&rngcclk>, <&hclkrng>;
|
|
clock-names = "rng", "apb_pclk";
|
|
};
|
|
|
|
rtc: rtc@101e8000 {
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
reg = <0x101e8000 0x1000>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <10>;
|
|
};
|
|
|
|
mmcsd: sdi@101f6000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
reg = <0x101f6000 0x1000>;
|
|
clocks = <&sdiclk>, <&pclksdi>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <22>;
|
|
max-frequency = <48000000>;
|
|
bus-width = <4>;
|
|
cap-mmc-highspeed;
|
|
cap-sd-highspeed;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
|
|
vmmc-supply = <&vmmc_regulator>;
|
|
};
|
|
};
|
|
};
|