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119f517362
This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: YT Shen <yt.shen@mediatek.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Mao Huang <littlecvr@chromium.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
241 lines
6.5 KiB
C
241 lines
6.5 KiB
C
/*
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* Copyright (c) 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drm/drmP.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include "mtk_drm_crtc.h"
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#include "mtk_drm_ddp_comp.h"
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#define DISP_REG_RDMA_INT_ENABLE 0x0000
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#define DISP_REG_RDMA_INT_STATUS 0x0004
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#define RDMA_TARGET_LINE_INT BIT(5)
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#define RDMA_FIFO_UNDERFLOW_INT BIT(4)
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#define RDMA_EOF_ABNORMAL_INT BIT(3)
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#define RDMA_FRAME_END_INT BIT(2)
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#define RDMA_FRAME_START_INT BIT(1)
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#define RDMA_REG_UPDATE_INT BIT(0)
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#define DISP_REG_RDMA_GLOBAL_CON 0x0010
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#define RDMA_ENGINE_EN BIT(0)
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#define DISP_REG_RDMA_SIZE_CON_0 0x0014
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#define DISP_REG_RDMA_SIZE_CON_1 0x0018
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#define DISP_REG_RDMA_TARGET_LINE 0x001c
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#define DISP_REG_RDMA_FIFO_CON 0x0040
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#define RDMA_FIFO_UNDERFLOW_EN BIT(31)
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#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
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#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
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/**
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* struct mtk_disp_rdma - DISP_RDMA driver structure
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* @ddp_comp - structure containing type enum and hardware resources
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* @crtc - associated crtc to report irq events to
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*/
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struct mtk_disp_rdma {
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struct mtk_ddp_comp ddp_comp;
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struct drm_crtc *crtc;
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};
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static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
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{
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struct mtk_disp_rdma *priv = dev_id;
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struct mtk_ddp_comp *rdma = &priv->ddp_comp;
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/* Clear frame completion interrupt */
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writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS);
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if (!priv->crtc)
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return IRQ_NONE;
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mtk_crtc_ddp_irq(priv->crtc, rdma);
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return IRQ_HANDLED;
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}
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static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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unsigned int tmp = readl(comp->regs + reg);
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tmp = (tmp & ~mask) | (val & mask);
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writel(tmp, comp->regs + reg);
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}
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static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
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struct drm_crtc *crtc)
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{
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struct mtk_disp_rdma *priv = container_of(comp, struct mtk_disp_rdma,
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ddp_comp);
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priv->crtc = crtc;
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rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
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RDMA_FRAME_END_INT);
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}
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static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
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{
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struct mtk_disp_rdma *priv = container_of(comp, struct mtk_disp_rdma,
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ddp_comp);
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priv->crtc = NULL;
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rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
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}
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static void mtk_rdma_start(struct mtk_ddp_comp *comp)
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{
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rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
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RDMA_ENGINE_EN);
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}
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static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
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{
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rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
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}
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static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
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unsigned int height, unsigned int vrefresh)
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{
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unsigned int threshold;
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unsigned int reg;
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rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
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rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
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/*
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* Enable FIFO underflow since DSI and DPI can't be blocked.
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* Keep the FIFO pseudo size reset default of 8 KiB. Set the
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* output threshold to 6 microseconds with 7/6 overhead to
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* account for blanking, and with a pixel depth of 4 bytes:
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*/
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threshold = width * height * vrefresh * 4 * 7 / 1000000;
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reg = RDMA_FIFO_UNDERFLOW_EN |
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RDMA_FIFO_PSEUDO_SIZE(SZ_8K) |
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RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
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writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
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}
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static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
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.config = mtk_rdma_config,
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.start = mtk_rdma_start,
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.stop = mtk_rdma_stop,
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.enable_vblank = mtk_rdma_enable_vblank,
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.disable_vblank = mtk_rdma_disable_vblank,
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};
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static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
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struct drm_device *drm_dev = data;
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int ret;
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ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
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if (ret < 0) {
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dev_err(dev, "Failed to register component %s: %d\n",
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dev->of_node->full_name, ret);
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return ret;
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}
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return 0;
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}
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static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
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struct drm_device *drm_dev = data;
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mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
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}
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static const struct component_ops mtk_disp_rdma_component_ops = {
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.bind = mtk_disp_rdma_bind,
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.unbind = mtk_disp_rdma_unbind,
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};
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static int mtk_disp_rdma_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_disp_rdma *priv;
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int comp_id;
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int irq;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA);
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if (comp_id < 0) {
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dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
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return comp_id;
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}
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ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
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&mtk_disp_rdma_funcs);
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if (ret) {
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dev_err(dev, "Failed to initialize component: %d\n", ret);
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return ret;
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}
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/* Disable and clear pending interrupts */
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writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE);
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writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS);
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ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
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IRQF_TRIGGER_NONE, dev_name(dev), priv);
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if (ret < 0) {
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dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
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return ret;
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}
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platform_set_drvdata(pdev, priv);
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ret = component_add(dev, &mtk_disp_rdma_component_ops);
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if (ret)
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dev_err(dev, "Failed to add component: %d\n", ret);
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return ret;
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}
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static int mtk_disp_rdma_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
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return 0;
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}
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static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
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{ .compatible = "mediatek,mt8173-disp-rdma", },
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{},
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};
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MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
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struct platform_driver mtk_disp_rdma_driver = {
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.probe = mtk_disp_rdma_probe,
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.remove = mtk_disp_rdma_remove,
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.driver = {
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.name = "mediatek-disp-rdma",
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.owner = THIS_MODULE,
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.of_match_table = mtk_disp_rdma_driver_dt_match,
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},
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};
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