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There are two files in the Documentation/trace directory relating to coresight, with more to follow, so create a Documentation/trace/coresight directory and move existing files there. Fixup index to reference new location. Update MAINTAINERS to reference this sub-directory rather than the individual files. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
193 lines
8.4 KiB
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193 lines
8.4 KiB
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==========================
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Coresight CPU Debug Module
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==========================
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:Author: Leo Yan <leo.yan@linaro.org>
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:Date: April 5th, 2017
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Introduction
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------------
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Coresight CPU debug module is defined in ARMv8-a architecture reference manual
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(ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
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debug module and it is mainly used for two modes: self-hosted debug and
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external debug. Usually the external debug mode is well known as the external
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debugger connects with SoC from JTAG port; on the other hand the program can
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explore debugging method which rely on self-hosted debug mode, this document
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is to focus on this part.
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The debug module provides sample-based profiling extension, which can be used
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to sample CPU program counter, secure state and exception level, etc; usually
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every CPU has one dedicated debug module to be connected. Based on self-hosted
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debug mechanism, Linux kernel can access these related registers from mmio
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region when the kernel panic happens. The callback notifier for kernel panic
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will dump related registers for every CPU; finally this is good for assistant
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analysis for panic.
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Implementation
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--------------
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- During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
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registers to decide if sample-based profiling is implemented or not. On some
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platforms this hardware feature is fully or partially implemented; and if
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this feature is not supported then registration will fail.
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- At the time this documentation was written, the debug driver mainly relies on
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information gathered by the kernel panic callback notifier from three
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sampling registers: EDPCSR, EDVIDSR and EDCIDSR: from EDPCSR we can get
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program counter; EDVIDSR has information for secure state, exception level,
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bit width, etc; EDCIDSR is context ID value which contains the sampled value
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of CONTEXTIDR_EL1.
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- The driver supports a CPU running in either AArch64 or AArch32 mode. The
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registers naming convention is a bit different between them, AArch64 uses
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'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
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'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
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use AArch64 naming convention.
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- ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
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register bits definition. So the driver consolidates two difference:
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If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
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but ARMv7-a defines "PCSR samples are offset by a value that depends on the
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instruction set state". For ARMv7-a, the driver checks furthermore if CPU
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runs with ARM or thumb instruction set and calibrate PCSR value, the
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detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
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C11.11.34 "DBGPCSR, Program Counter Sampling Register".
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If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
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no offset applied and do not sample the instruction set state in AArch32
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state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
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in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
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state EDPCSR is sampled and no offset are applied.
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Clock and power domain
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----------------------
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Before accessing debug registers, we should ensure the clock and power domain
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have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
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Debug registers', the debug registers are spread into two domains: the debug
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domain and the CPU domain.
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::
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+---------------+
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+----------+--+ |
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dbg_clock -->| |**| |<-- cpu_clock
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| Debug |**| CPU |
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dbg_power_domain -->| |**| |<-- cpu_power_domain
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+----------+--+ |
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+---------------+
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For debug domain, the user uses DT binding "clocks" and "power-domains" to
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specify the corresponding clock source and power supply for the debug logic.
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The driver calls the pm_runtime_{put|get} operations as needed to handle the
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debug power domain.
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For CPU domain, the different SoC designs have different power management
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schemes and finally this heavily impacts external debug module. So we can
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divide into below cases:
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- On systems with a sane power controller which can behave correctly with
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respect to CPU power domain, the CPU power domain can be controlled by
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register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ
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to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
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of CPU power down. As result, this can ensure the CPU power domain is
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powered on properly during the period when access debug related registers;
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- Some designs will power down an entire cluster if all CPUs on the cluster
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are powered down - including the parts of the debug registers that should
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remain powered in the debug power domain. The bits in EDPRCR are not
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respected in these cases, so these designs do not support debug over
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power down in the way that the CoreSight / Debug designers anticipated.
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This means that even checking EDPRSR has the potential to cause a bus hang
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if the target register is unpowered.
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In this case, accessing to the debug registers while they are not powered
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is a recipe for disaster; so we need preventing CPU low power states at boot
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time or when user enable module at the run time. Please see chapter
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"How to use the module" for detailed usage info for this.
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Device Tree Bindings
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--------------------
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See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
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How to use the module
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---------------------
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If you want to enable debugging functionality at boot time, you can add
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"coresight_cpu_debug.enable=1" to the kernel command line parameter.
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The driver also can work as module, so can enable the debugging when insmod
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module::
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# insmod coresight_cpu_debug.ko debug=1
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When boot time or insmod module you have not enabled the debugging, the driver
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uses the debugfs file system to provide a knob to dynamically enable or disable
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debugging:
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To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable::
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# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
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To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable::
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# echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable
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As explained in chapter "Clock and power domain", if you are working on one
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platform which has idle states to power off debug logic and the power
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controller cannot work well for the request from EDPRCR, then you should
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firstly constraint CPU idle states before enable CPU debugging feature; so can
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ensure the accessing to debug logic.
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If you want to limit idle states at boot time, you can use "nohlt" or
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"cpuidle.off=1" in the kernel command line.
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At the runtime you can disable idle states with below methods:
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It is possible to disable CPU idle states by way of the PM QoS
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subsystem, more specifically by using the "/dev/cpu_dma_latency"
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interface (see Documentation/power/pm_qos_interface.rst for more
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details). As specified in the PM QoS documentation the requested
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parameter will stay in effect until the file descriptor is released.
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For example::
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# exec 3<> /dev/cpu_dma_latency; echo 0 >&3
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...
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Do some work...
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...
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# exec 3<>-
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The same can also be done from an application program.
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Disable specific CPU's specific idle state from cpuidle sysfs (see
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Documentation/admin-guide/pm/cpuidle.rst)::
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# echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable
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Output format
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-------------
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Here is an example of the debugging output format::
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ARM external debug module:
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coresight-cpu-debug 850000.debug: CPU[0]:
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coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
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coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
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coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
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coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
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coresight-cpu-debug 852000.debug: CPU[1]:
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coresight-cpu-debug 852000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
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coresight-cpu-debug 852000.debug: EDPCSR: debug_notifier_call+0x23c/0x358
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coresight-cpu-debug 852000.debug: EDCIDSR: 00000000
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coresight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
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