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5a799b824b
764f4e4e33
(sh: clkfwk: Use shared sh_clk_div_enable/disable())
shared enable/disable funcions for div4/div6.
But new sh_clk_div_enable() didn't care sh_clk_div_set_rate()
which is required on div6 clock.
This patch fixes it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
455 lines
10 KiB
C
455 lines
10 KiB
C
/*
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* Helper routines for SuperH Clock Pulse Generator blocks (CPG).
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 - 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#define CPG_CKSTP_BIT BIT(8)
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static unsigned int sh_clk_read(struct clk *clk)
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{
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if (clk->flags & CLK_ENABLE_REG_8BIT)
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return ioread8(clk->mapped_reg);
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else if (clk->flags & CLK_ENABLE_REG_16BIT)
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return ioread16(clk->mapped_reg);
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return ioread32(clk->mapped_reg);
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}
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static void sh_clk_write(int value, struct clk *clk)
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{
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if (clk->flags & CLK_ENABLE_REG_8BIT)
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iowrite8(value, clk->mapped_reg);
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else if (clk->flags & CLK_ENABLE_REG_16BIT)
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iowrite16(value, clk->mapped_reg);
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else
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iowrite32(value, clk->mapped_reg);
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}
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static int sh_clk_mstp_enable(struct clk *clk)
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{
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sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
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return 0;
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}
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static void sh_clk_mstp_disable(struct clk *clk)
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{
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sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);
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}
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static struct sh_clk_ops sh_clk_mstp_clk_ops = {
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.enable = sh_clk_mstp_enable,
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.disable = sh_clk_mstp_disable,
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.recalc = followparent_recalc,
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};
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int __init sh_clk_mstp_register(struct clk *clks, int nr)
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{
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struct clk *clkp;
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int ret = 0;
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int k;
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &sh_clk_mstp_clk_ops;
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ret |= clk_register(clkp);
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}
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return ret;
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}
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/*
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* Div/mult table lookup helpers
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*/
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static inline struct clk_div_table *clk_to_div_table(struct clk *clk)
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{
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return clk->priv;
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}
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static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)
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{
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return clk_to_div_table(clk)->div_mult_table;
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}
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/*
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* Common div ops
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*/
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static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_table_round(clk, clk->freq_table, rate);
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}
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static unsigned long sh_clk_div_recalc(struct clk *clk)
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{
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struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
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unsigned int idx;
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, clk->arch_flags ? &clk->arch_flags : NULL);
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idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_div_table *dt = clk_to_div_table(clk);
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unsigned long value;
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int idx;
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idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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value = sh_clk_read(clk);
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value &= ~(clk->div_mask << clk->enable_bit);
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value |= (idx << clk->enable_bit);
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sh_clk_write(value, clk);
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/* XXX: Should use a post-change notifier */
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if (dt->kick)
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dt->kick(clk);
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return 0;
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}
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static int sh_clk_div_enable(struct clk *clk)
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{
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if (clk->div_mask == SH_CLK_DIV6_MSK) {
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int ret = sh_clk_div_set_rate(clk, clk->rate);
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if (ret < 0)
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return ret;
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}
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sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
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return 0;
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}
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static void sh_clk_div_disable(struct clk *clk)
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{
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unsigned int val;
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val = sh_clk_read(clk);
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val |= CPG_CKSTP_BIT;
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/*
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* div6 clocks require the divisor field to be non-zero or the
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* above CKSTP toggle silently fails. Ensure that the divisor
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* array is reset to its initial state on disable.
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*/
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if (clk->flags & CLK_MASK_DIV_ON_DISABLE)
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val |= clk->div_mask;
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sh_clk_write(val, clk);
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}
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static struct sh_clk_ops sh_clk_div_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.set_rate = sh_clk_div_set_rate,
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.round_rate = sh_clk_div_round_rate,
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};
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static struct sh_clk_ops sh_clk_div_enable_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.set_rate = sh_clk_div_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div_enable,
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.disable = sh_clk_div_disable,
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};
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static int __init sh_clk_init_parent(struct clk *clk)
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{
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u32 val;
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if (clk->parent)
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return 0;
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if (!clk->parent_table || !clk->parent_num)
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return 0;
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if (!clk->src_width) {
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pr_err("sh_clk_init_parent: cannot select parent clock\n");
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return -EINVAL;
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}
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val = (sh_clk_read(clk) >> clk->src_shift);
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val &= (1 << clk->src_width) - 1;
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if (val >= clk->parent_num) {
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pr_err("sh_clk_init_parent: parent table size failed\n");
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return -EINVAL;
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}
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clk_reparent(clk, clk->parent_table[val]);
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if (!clk->parent) {
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pr_err("sh_clk_init_parent: unable to set parent");
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return -EINVAL;
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}
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return 0;
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}
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static int __init sh_clk_div_register_ops(struct clk *clks, int nr,
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struct clk_div_table *table, struct sh_clk_ops *ops)
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{
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struct clk *clkp;
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void *freq_table;
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int nr_divs = table->div_mult_table->nr_divisors;
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int freq_table_size = sizeof(struct cpufreq_frequency_table);
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int ret = 0;
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int k;
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freq_table_size *= (nr_divs + 1);
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freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
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if (!freq_table) {
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pr_err("%s: unable to alloc memory\n", __func__);
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return -ENOMEM;
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}
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = ops;
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clkp->priv = table;
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clkp->freq_table = freq_table + (k * freq_table_size);
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clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
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ret = clk_register(clkp);
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if (ret == 0)
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ret = sh_clk_init_parent(clkp);
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}
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return ret;
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}
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/*
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* div6 support
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*/
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static int sh_clk_div6_divisors[64] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
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};
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static struct clk_div_mult_table div6_div_mult_table = {
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.divisors = sh_clk_div6_divisors,
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.nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
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};
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static struct clk_div_table sh_clk_div6_table = {
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.div_mult_table = &div6_div_mult_table,
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};
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static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
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u32 value;
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int ret, i;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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value = sh_clk_read(clk) &
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~(((1 << clk->src_width) - 1) << clk->src_shift);
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sh_clk_write(value | (i << clk->src_shift), clk);
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/* Rebuild the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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return 0;
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}
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static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div_set_rate,
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.enable = sh_clk_div_enable,
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.disable = sh_clk_div_disable,
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.set_parent = sh_clk_div6_set_parent,
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};
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int __init sh_clk_div6_register(struct clk *clks, int nr)
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{
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return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
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&sh_clk_div_enable_clk_ops);
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}
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int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
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{
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return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
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&sh_clk_div6_reparent_clk_ops);
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}
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/*
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* div4 support
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*/
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static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
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u32 value;
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int ret;
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/* we really need a better way to determine parent index, but for
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* now assume internal parent comes with CLK_ENABLE_ON_INIT set,
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* no CLK_ENABLE_ON_INIT means external clock...
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*/
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if (parent->flags & CLK_ENABLE_ON_INIT)
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value = sh_clk_read(clk) & ~(1 << 7);
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else
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value = sh_clk_read(clk) | (1 << 7);
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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sh_clk_write(value, clk);
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/* Rebiuld the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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return 0;
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}
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static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.set_rate = sh_clk_div_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div_enable,
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.disable = sh_clk_div_disable,
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.set_parent = sh_clk_div4_set_parent,
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};
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int __init sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops);
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}
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int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div_register_ops(clks, nr, table,
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&sh_clk_div_enable_clk_ops);
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}
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int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div_register_ops(clks, nr, table,
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&sh_clk_div4_reparent_clk_ops);
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}
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/* FSI-DIV */
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static unsigned long fsidiv_recalc(struct clk *clk)
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{
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u32 value;
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value = __raw_readl(clk->mapping->base);
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value >>= 16;
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if (value < 2)
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return clk->parent->rate;
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return clk->parent->rate / value;
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}
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static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_div_range_round(clk, 1, 0xffff, rate);
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}
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static void fsidiv_disable(struct clk *clk)
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{
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__raw_writel(0, clk->mapping->base);
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}
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static int fsidiv_enable(struct clk *clk)
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{
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u32 value;
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value = __raw_readl(clk->mapping->base) >> 16;
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if (value < 2)
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return 0;
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__raw_writel((value << 16) | 0x3, clk->mapping->base);
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return 0;
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}
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static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
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{
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int idx;
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idx = (clk->parent->rate / rate) & 0xffff;
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if (idx < 2)
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__raw_writel(0, clk->mapping->base);
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else
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__raw_writel(idx << 16, clk->mapping->base);
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return 0;
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}
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static struct sh_clk_ops fsidiv_clk_ops = {
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.recalc = fsidiv_recalc,
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.round_rate = fsidiv_round_rate,
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.set_rate = fsidiv_set_rate,
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.enable = fsidiv_enable,
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.disable = fsidiv_disable,
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};
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int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
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{
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struct clk_mapping *map;
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int i;
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for (i = 0; i < nr; i++) {
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map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
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if (!map) {
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pr_err("%s: unable to alloc memory\n", __func__);
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return -ENOMEM;
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}
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/* clks[i].enable_reg came from SH_CLK_FSIDIV() */
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map->phys = (phys_addr_t)clks[i].enable_reg;
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map->len = 8;
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clks[i].enable_reg = 0; /* remove .enable_reg */
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clks[i].ops = &fsidiv_clk_ops;
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clks[i].mapping = map;
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clk_register(&clks[i]);
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}
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return 0;
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}
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