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71b9114d2c
s3c24xx and s3c64xx have a lot in common, but are split across three
separate directories, which makes the interaction of the header files
more complicated than necessary.
Move all three directories into a new mach-s3c, with a minimal
set of changes to each file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[krzk: Rebase, add s3c24xx and s3c64xx suffix to several files, add SPDX
headers to new files, remove plat-samsung from MAINTAINERS]
Co-developed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
https://lore.kernel.org/r/20200806182059.2431-39-krzk@kernel.org
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2009 Andy Green <andy@warmcat.com>
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*
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* S3C64XX SROM definitions
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*/
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#ifndef __MACH_S3C64XX_REGS_SROM_H
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#define __MACH_S3C64XX_REGS_SROM_H __FILE__
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#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
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#define S3C64XX_SROM_BW S3C64XX_SROMREG(0)
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#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4)
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#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8)
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#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc)
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#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10)
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#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14)
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#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18)
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/*
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* one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
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*/
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#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
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#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
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#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
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#define S3C64XX_SROM_BW__CS_MASK 0xf
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#define S3C64XX_SROM_BW__NCS0__SHIFT 0
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#define S3C64XX_SROM_BW__NCS1__SHIFT 4
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#define S3C64XX_SROM_BW__NCS2__SHIFT 8
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#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc
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#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10
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/*
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* applies to same to BCS0 - BCS4
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*/
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#define S3C64XX_SROM_BCX__PMC__SHIFT 0
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#define S3C64XX_SROM_BCX__PMC__MASK 3
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#define S3C64XX_SROM_BCX__TACP__SHIFT 4
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#define S3C64XX_SROM_BCX__TACP__MASK 0xf
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#define S3C64XX_SROM_BCX__TCAH__SHIFT 8
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#define S3C64XX_SROM_BCX__TCAH__MASK 0xf
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#define S3C64XX_SROM_BCX__TCOH__SHIFT 12
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#define S3C64XX_SROM_BCX__TCOH__MASK 0xf
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#define S3C64XX_SROM_BCX__TACC__SHIFT 16
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#define S3C64XX_SROM_BCX__TACC__MASK 0x1f
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#define S3C64XX_SROM_BCX__TCOS__SHIFT 24
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#define S3C64XX_SROM_BCX__TCOS__MASK 0xf
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#define S3C64XX_SROM_BCX__TACS__SHIFT 28
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#define S3C64XX_SROM_BCX__TACS__MASK 0xf
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#endif /* __MACH_S3C64XX_REGS_SROM_H */
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