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2cbee26e5d
Expose the high performance PLL as a regular Linux clock, so the PCIe PHY can use it when there is no external refclock provided. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
43 lines
1.0 KiB
Plaintext
43 lines
1.0 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "i.MX SoC drivers"
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config IMX_GPCV2_PM_DOMAINS
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bool "i.MX GPCv2 PM domains"
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depends on ARCH_MXC || (COMPILE_TEST && OF)
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depends on PM
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select PM_GENERIC_DOMAINS
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select REGMAP_MMIO
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default y if SOC_IMX7D
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config SOC_IMX8M
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bool "i.MX8M SoC family support"
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depends on ARCH_MXC || COMPILE_TEST
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default ARCH_MXC && ARM64
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select SOC_BUS
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select ARM_GIC_V3 if ARCH_MXC && ARCH_MULTI_V7
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help
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If you say yes here you get support for the NXP i.MX8M family
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support, it will provide the SoC info like SoC family,
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ID and revision etc.
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config SOC_IMX9
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tristate "i.MX9 SoC family support"
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depends on ARCH_MXC || COMPILE_TEST
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default ARCH_MXC && ARM64
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select SOC_BUS
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help
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If you say yes here, you get support for the NXP i.MX9 family
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config IMX8M_BLK_CTRL
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bool
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default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS
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depends on PM_GENERIC_DOMAINS
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depends on COMMON_CLK
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config IMX9_BLK_CTRL
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bool
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default SOC_IMX9 && IMX_GPCV2_PM_DOMAINS
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depends on PM_GENERIC_DOMAINS
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endmenu
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