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118c07aeda
mbus is the memory bus clock, and it is present on both sun5i and sun7i machines. Its register layout is compatible with the mod0 one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
455 lines
10 KiB
Plaintext
455 lines
10 KiB
Plaintext
/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&intc>;
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a8";
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};
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};
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memory {
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reg = <0x40000000 0x20000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clock-frequency = <24000000>;
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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pll5: pll5@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: pll6@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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};
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axi_gates: axi_gates@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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};
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ahb_gates: ahb_gates@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
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"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
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"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
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"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
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"ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
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"ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
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"ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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};
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apb0_gates: apb0_gates@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
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"apb0_ir", "apb0_keypad";
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};
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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};
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apb1_gates: apb1_gates@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20098 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2009c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ss";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi2";
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};
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ir0_clk: clk@01c200b0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200b0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mbus";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <55>;
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clocks = <&ahb_gates 17>;
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status = "disabled";
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};
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mdio@01c0b080 {
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compatible = "allwinner,sun4i-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sun4i-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun5i-a10s-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <28>;
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clocks = <&apb0_gates 5>;
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gpio-controller;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#gpio-cells = <3>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PB19", "PB20";
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allwinner,function = "uart0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart2_pins_a: uart2@0 {
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allwinner,pins = "PC18", "PC19";
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allwinner,function = "uart2";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart3_pins_a: uart3@0 {
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allwinner,pins = "PG9", "PG10";
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allwinner,function = "uart3";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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emac_pins_a: emac0@0 {
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allwinner,pins = "PA0", "PA1", "PA2",
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"PA3", "PA4", "PA5", "PA6",
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"PA7", "PA8", "PA9", "PA10",
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"PA11", "PA12", "PA13", "PA14",
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"PA15", "PA16";
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allwinner,function = "emac";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c0_pins_a: i2c0@0 {
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allwinner,pins = "PB0", "PB1";
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allwinner,function = "i2c0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c1_pins_a: i2c1@0 {
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allwinner,pins = "PB15", "PB16";
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allwinner,function = "i2c1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c2_pins_a: i2c2@0 {
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allwinner,pins = "PB17", "PB18";
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allwinner,function = "i2c2";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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};
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timer@01c20c00 {
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compatible = "allwinner,sun4i-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <22>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@01c20c90 {
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compatible = "allwinner,sun4i-wdt";
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reg = <0x01c20c90 0x10>;
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};
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sid: eeprom@01c23800 {
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compatible = "allwinner,sun4i-sid";
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reg = <0x01c23800 0x10>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 16>;
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 17>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 18>;
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 19>;
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status = "disabled";
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};
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i2c0: i2c@01c2ac00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <7>;
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clocks = <&apb1_gates 0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@01c2b000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <8>;
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clocks = <&apb1_gates 1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c2: i2c@01c2b400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <9>;
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clocks = <&apb1_gates 2>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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};
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};
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